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| 型號(hào)： | EVAL-ADUC7039QSPZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 85/92頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL FOR ADUC7039 |
| 設(shè)計(jì)資源： | ADuC7039QSPZ Gerber Files EVAL-ADuC7039 Schematic & Brd Outline |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | QuickStart™ PLUS 套件 |
| 類型： | MCU |
| 適用于相關(guān)產(chǎn)品： | ADuC7039 |
| 所含物品： | 板 |
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ADuC7039
Data Sheet
Rev. D | Page 86 of 92
Table 61. LINCON MMR Bit Designations
Bits
Description
15 to 13
Reserved.
12
LIN bypass bit.
This bit is set to 1 by user code to take control of the LIN transceiver alone, for LIN conformance test.
This bit is cleared to 0 by user code to operate in normal mode.
11
LIN enable bit.
This bit is set to 1 by user code to enable the LIN interface.
This bit is cleared to 0 by user code to disable the LIN interface or to reset the interface.
10
UART enable bit.
This bit is set by user code to allow transmission without receiving the frame header, for test purposes.
This bit is cleared by user code for normal mode operation.
9
Timing of sync symbol, Bit 0 (not require in a single slave system).
Ensure that if a second break is transmitted it is recognized as such and not timed as part of the sync symbol. If the start
symbol is more than the number of clock ticks dictated by this bit, the device assumes it is now receiving a break and continues
to count the low cycle to see if the break meets the minimum time required for a break as defined in the LINBK MMR.
Set by the user. The first bit of the sync symbol must be less than 750 core clocks (73 s).
This bit is cleared by the user to disable this functionality.
8
Send checksum.
This bit is set by the user to transmit the checksum automatically. This bit must be set after the last data byte to transmit what
is written in LINDAT and after the transmit ready bit is set.
This bit is cleared automatically by hardware when the checksum is sent.
7
Checksum calculation.
This bit is set by the user to calculate automatically a classic checksum (PID excluded).
This bit is cleared by the user to calculate an enhanced checksum (PID included).
Modifying the value of this bit during communication, for example after receiving a PID, resets the checksum.
6
Collision detect and transmit complete interrupt mask.
This bit is set by the user to disable the collision detect and transmit complete interrupt.
This bit is cleared by the user to enable the collision detect and transmit complete interrupt.
When the interrupt is enabled, all occurrences of collision detected causes an interrupt to occur and the collision status bit to
be asserted, regardless of the state of the transmit finished bit. When masking is enabled, once the transmit is finished,
asserted occurrences of collision detected are masked and do not cause an interrupt to occur or the collision detected status
bit to be set. Even if this masking bit has been set by the user if transmit finished has not been asserted by the device, collisions
cause an interrupt to occur and the collision detected status bit to be set.
5
Negative edge maximum error interrupt mask.
This bit is set by the user to disable the negative edge maximum error interrupt.
This bit is cleared by the user to enable the negative edge maximum error interrupt. An interrupt is generated if the negative
edge counter counts more than 57 edges in a frame.
4
Collision detect interrupt mask.
This bit is set by the user to disable the collision detect interrupt.
This bit is cleared by the user to enable the collision detect interrupt.
3
Break received interrupt mask.
This bit is set by the user to disable the break symbol receive interrupt.
This bit is cleared by the user to enable the break symbol receive interrupt.
2
Transmit complete interrupt mask.
This bit is set by the user to disable the transmit complete interrupt.
This bit is cleared by the user to enable the transmit complete interrupt.
1
Transmit ready interrupt mask.
This bit is set by the user to disable the transmit ready interrupt. Set automatically when LINCON[8] is set.
This bit is cleared by the user to enable the transmit ready interrupt.
0
Receive/transmit mode.
This bit is set by user code to transmit data bytes after decoding the PID.
This bit is cleared automatically when a break symbol is received.
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