參數(shù)資料
型號： EVAL-ADUC7039QSPZ
廠商： Analog Devices Inc
文件頁數(shù)： 65/92頁
文件大?。?/td> 0K
描述： BOARD EVAL FOR ADUC7039
設(shè)計資源： ADuC7039QSPZ Gerber Files
EVAL-ADuC7039 Schematic & Brd Outline
標準包裝： 1
系列： QuickStart™ PLUS 套件
類型： MCU
適用于相關(guān)產(chǎn)品： ADuC7039
所含物品： 板
ADuC7039
Data Sheet
Rev. D | Page 68 of 92
Figure 27. Timer2 Block Diagram
Table 48. T2CON MMR Bit Designations
Bit
Description
15 to 9
Reserved. These bits are reserved and should be written as 0 by user code.
8
Count up/count down enable.
This bit is set by user code to configure Timer2 to count up.
This bit is cleared by user code to configure Timer2 to count down.
7
Timer2 enable.
This bit is set by user code to enable Timer2.
This bit is cleared by user code to disable Timer2.
6
Timer2 operating mode.
This bit is set by user code to configure Timer2 to operate in periodic mode.
This bit is cleared by user to configure Timer2 to operate in free running mode.
5
Watchdog timer mode enable.
This bit is set by user code to enable watchdog mode.
This bit is cleared by user code to disable watchdog mode.
4
Reserved. This bit is reserved and should be written as 0 by user code.
3 to 2
Timer2 clock prescaler.
00 = source clock/1 (default).
01 = source clock/16.
10 = source clock/256.
11 = reserved.
1
Watchdog timer IRQ enable.
This bit is set by user code to produce an IRQ instead of a reset when the watchdog reaches 0.
This bit is cleared by user code to disable the IRQ option.
0
PD_OFF.
This bit is set by the user code to stop Timer2 when the peripherals are powered down using Bit 4 in the POWCON MMR.
This bit is cleared by the user code to enable Timer2 when the peripherals are powered down using Bit 4 in the
POWCON MMR.
PRESCALER
1, 16, 256
TIMER2 IRQ
WATCHDOG RESET
16-BIT
UP/DOWN COUNTER
LOW POWER
OSCILLATOR
16-BIT LOAD
TIMER2
VALUE
08463-
024
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