參數(shù)資料
型號: EVAL-ADUC7039QSPZ
廠商: Analog Devices Inc
文件頁數(shù): 11/92頁
文件大?。?/td> 0K
描述: BOARD EVAL FOR ADUC7039
設(shè)計資源: ADuC7039QSPZ Gerber Files
EVAL-ADuC7039 Schematic & Brd Outline
標(biāo)準(zhǔn)包裝: 1
系列: QuickStart™ PLUS 套件
類型: MCU
適用于相關(guān)產(chǎn)品: ADuC7039
所含物品:
Data Sheet
ADuC7039
Rev. D | Page 19 of 92
Command Sequence for Executing a Mass Erase
Given the significance of the mass erase command, a specific code sequence must be executed to initiate this operation.
1. Ensure FEESTA is cleared.
2. Set Bit 3 in FEEMOD.
3. Write 0xFFC3 in FEEADR.
4. Write 0x3CFF in FEEDAT.
5. Run the mass erase command (0x06) in FEECON.
Command Sequence Example
The command sequence for excecuting a mass erase is illustrated in the following example:
int a = FEESTA;
// Ensure FEESTA is cleared
FEEMOD = 0x08
FEEADR = 0xFFC3
FEEDAT = 0x3CFF
FEECON = 0x06;
//Mass erase command
while (FEESTA & 0x04){}
//Wait for command to finish
FEESTA Register
Name:
FEESTA
Address:
0xFFFF0E00
Default Value: 0xXXX0
Access:
Read only
Function:
This 16-bit, read-only register can be read by user code and reflects the current status of the Flash/EE memory controller.
Table 11. FEESTA MMR Bit Designation
Bit
Description
15 to 4
Reserved.
3
Flash/EE interrupt status bit.
This bit is set automatically when an interrupt occurs, that is, when a command is complete and the Flash/EE interrupt
enable bit in the FEEMOD register is set.
This bit is cleared automatically when the FEESTA register is read by user code.
2
Flash/EE controller busy.
This bit is set automatically when the Flash/EE controller is busy.
This bit is cleared automatically when the controller is not busy.
1
Command fail.
This bit is set automatically when a command written to FEECON completes unsuccessfully.
This bit is cleared automatically when the FEESTA register is read by user code.
0
Command successful.
This bit is set automatically by MCU when a command is completed successfully.
This bit is cleared automatically when the FEESTA register is read by user code.
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