VDD
參數(shù)資料
型號(hào)： EVAL-ADUC7039QSPZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 34/92頁(yè)
文件大?。?/td> 0K
描述： BOARD EVAL FOR ADUC7039
設(shè)計(jì)資源： ADuC7039QSPZ Gerber Files
EVAL-ADuC7039 Schematic & Brd Outline
標(biāo)準(zhǔn)包裝： 1
系列： QuickStart™ PLUS 套件
類型： MCU
適用于相關(guān)產(chǎn)品： ADuC7039
所含物品： 板
ADuC7039
Data Sheet
Rev. D | Page 4 of 92
SPECIFICATIONS
ELECTRICAL SPECIFICATIONS
VDD = 3.5 V to 18 V, VREF= 1.2 V internal reference, fCORE = 20.48 MHz driven from on-chip precision oscillator, all specifications TA = 40°C to
+115°C, unless otherwise noted.
Table 1.
Parameter
Test Conditions/Comments
Min
Typ
Max
Unit
ADC SPECIFICATIONS
Conversion Rate1
ADC normal operating mode
10
1000
Hz
ADC low power mode, chop on
10
650
Hz
Current Channel
No Missing Codes1
Valid for all ADC update rates and ADC modes
16
Bits
Integral Nonlinearity1, 2
±10
±60
ppm of FSR
Offset Error1, 2, 3
Chop off, external short, after user system calibration,
1 LSB = (36.6/gain) V
10
±3
+10
LSB
Offset Error1, 3
Chop on, external short, low power mode,
MCU powered down
+250
±50
300
nV
Offset Error1, 3
Chop on, external short, after user system calibration
Tested at CD = 0, VDD = 18 V
0
3.0
V
Offset Error1, 3
Chop on, external short, after user system calibration
Tested at CD = 0, VDD = 4 V
±0.5
V
Offset Error Drift1, 2, 4
Chop off, gains of 8 to 64, normal mode
±0.03
LSB/°C
Offset Error Drift1, 4
Chop off, valid for ADC gain of 512
±30
nV/°C
Offset Error Drift1, 4
Chop on
±5
nV/°C
Total Gain Error1, 3, 5, 6
Factory calibrated at a gain of 4; normal mode
0.5
±0.1
+0.5
%
Low power mode
1
±0.2
+1
%
Gain Drift1, 7
±3
ppm/°C
PGA Gain Mismatch Error
±0.1
%
Output Noise1
10 Hz update rate, gain = 512, chop enabled
100
150
nV rms
1 kHz update rate, gain = 512, ADCFLT = 0x0007
0.6
0.9
V rms
1 kHz update rate, gain = 32, ADCFLT = 0x0007
0.8
1.2
V rms
1 kHz update rate, gain = 8, ADCFLT = 0x8101
2.1
4.1
V rms
1 kHz update rate, gain = 8, ADCFLT = 0x0007
1.6
2.4
V rms
1 kHz update rate, gain = 4, ADCFLT = 0x0007
2.6
3.9
V rms
ADC low power mode, 250Hz update rate, chop enable,
gain = 512
0.6
0.9
V rms
Voltage Channel8
No Missing Codes1
Valid at all ADC update rates
16
Bits
Integral Nonlinearity1
±10
±60
ppm of FSR
Offset Error1, 3
Chop off, 1 LSB = 439.5 V, after two point calibration
10
±1
+10
LSB
Offset Error1, 3
Chop on, after two point calibration
1
±0.3
+1
LSB
Offset Error Drift4
Chop off
±0.03
LSB/°C
Total Gain Error1, 3, 5, 6
Includes resistor mismatch
0.25
±0.06
+0.25
%
Total Gain Error1, 3, 5, 6
Temperature range = 25°C to +65°C
0.15
±0.03
+0.15
%
Gain Drift1, 7
Includes resistor mismatch drift
±3
ppm/°C
Output Noise1, 9
10 Hz update rate, chop on
60
90
V rms
1 kHz update rate, ADCFLT = 0x0007
180
270
V rms
Temperature Channel
No Missing Codes1
Valid at all ADC update rates
16
Bits
Integral Nonlinearity1
±10
±60
ppm of FSR
Offset Error3, 10
Chop off, 1 LSB = 19.84 μV (in unipolar mode)
10
±3
+10
LSB
Offset Error1, 3
Chop on
5
+1
+5
LSB
Offset Error Drift1
Chop off
0.03
LSB/°C
Total Gain Error1, 3, 10
VREF = (REG_AVDD, GND_SW)/2
0.25
±0.06
+0.25
%
Gain Drift1
3
ppm/°C
Output Noise1
1 kHz update rate
7.5
11.25
V rms
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