參數(shù)資料
型號： EVAL-ADUC7039QSPZ
廠商： Analog Devices Inc
文件頁數(shù)： 56/92頁
文件大?。?/td> 0K
描述： BOARD EVAL FOR ADUC7039
設(shè)計資源： ADuC7039QSPZ Gerber Files
EVAL-ADuC7039 Schematic & Brd Outline
標準包裝： 1
系列： QuickStart™ PLUS 套件
類型： MCU
適用于相關(guān)產(chǎn)品： ADuC7039
所含物品： 板
ADuC7039
Data Sheet
Rev. D | Page 6 of 92
Parameter
Test Conditions/Comments
Min
Typ
Max
Unit
ON-CHIP OSCILLATORS
Low Power Oscillator
128
kHz
Accuracy
After user calibration at nominal supply and room
temperature; includes drift data from 1000 hr life-test
3
+3
%
Precision Oscillator
128
kHz
Accuracy
After run time calibration
1
+1
%
MCU CLOCK RATE1
Default setting
10.24
MHz
MCU START-UP TIME1
At Power-On
Includes kernel power-on execution time
25
ms
After Reset Event
Includes kernel power-on execution time
5
ms
From MCU Power-Down
Oscillator running
2
ms
Internal PLL Lock Time
1
ms
LIN I/O GENERAL
Baud Rate
1000
20,000
Bits/sec
VDD
Supply voltage range for which the LIN interface is functional
7
18
V
Input Capacitance1
5.5
pF
LIN Comparator Response Time1
Using 22 Ω resistor
38
90
s
LIN DC PARAMETERS
ILIN DOM MAX
Current limit for driver when LIN bus is in dominant state;
VBAT = VBAT (maximum)
40
200
mA
ILIN_PAS_REC1
Driver off; 7.0 V < VBUS < 18 V; VDD = VLIN 0.7 V
20
A
ILIN_PAS_DOM1
Input leakage, VLIN = 0 V
1
mA
ILIN_NO_GND1, 20
Control unit disconnected from ground, GND = VDD;
0 V < VLIN < 18 V; VBAT = 12 V
1
+1
mA
IBUS_NO_BAT1
VBAT disconnected, VDD = GND, 0 V < VBUS < 18 V
100
A
VLIN_DOM1
LIN receiver dominant state, VDD > 7.0 V
0.4 VDD
V
VLIN_REC1
LIN receiver recessive state, VDD > 7.0 V
0.6 VDD
V
VLIN_CNT1
LIN receiver center voltage, VDD > 7.0 V
0.475 VDD
0.5 VDD
0.525 VDD
V
VHYS1
LIN receiver hysteresis voltage
0.175 VDD
V
VLIN_DOM_DRV_LOSUP1
LIN dominant output voltage; VDD = 7.0 V
RL 500 Ω
1.2
V
RL 1000 Ω
0.6
V
VLIN_DOM_DRV_HISUP1
LIN dominant output voltage; VDD = 18 V
RL 500 Ω
2
V
RL 1000 Ω
0.8
V
VLIN_RECESSIVE1
LIN recessive output voltage
0.8 VDD
V
VBAT Shift20
0
0.115 VDD
V
GND Shift20
0
0.115 VDD
V
RSLAVE
Slave termination resistance
20
30
47
kΩ
VSERIAL DIODE20
Voltage drop at the serial diode, DSer_Int
0.4
0.7
1
V
LIN AC PARAMETERS1
Bus load conditions (CBUS||RBUS):
1 nF||1 kΩ; 6.8 nF||660 Ω; 10 nF||500 Ω
D1
Duty Cycle 1
0.396
THREC(MAX) = 0.744 × VBAT
THDOM(MAX) = 0.581 × VBAT
VSUP = 7.0 V … 18 V; tBIT = 50 s
D1 = tBUS_REC(MIN)/(2 × tBIT)
D2
Duty Cycle 2
0.581
THREC(MIN) = 0.284 × VBAT
THDOM(MIN) = 0.422 × VBAT
VSUP = 7.0 V … 18 V; tBIT = 50 s
D2 = tBUS_REC(MAX)/(2 × tBIT)
THREC(MAX) = 0.778 × VBAT
0.417
THDOM(MAX) = 0.616 × VBAT
VDD = 7.0 V ... 18 V
tBIT = 96 s
D3 = tBUS_REC(MIN)/(2 × tBIT)
THREC(min) = 0.389 × VBAT
0.590
THDOM(min) = 0.251 × VBAT
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