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| 型號： | EVAL-ADUC7039QSPZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 80/92頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL FOR ADUC7039 |
| 設計資源： | ADuC7039QSPZ Gerber Files EVAL-ADuC7039 Schematic & Brd Outline |
| 標準包裝： | 1 |
| 系列： | QuickStart™ PLUS 套件 |
| 類型： | MCU |
| 適用于相關產品： | ADuC7039 |
| 所含物品： | 板 |
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Data Sheet
ADuC7039
Rev. D | Page 81 of 92
High Voltage Status Register
Name:
HVSTA
Address:
Indirectly addressed via the HVCON high voltage interface
Default Value: 0x00
Access:
Read only, this register should only be read on a high voltage interrupt
Function:
This 8-bit, read-only register reflects the state of the low voltage flag and the LIN short circuit interrupt status. This
register is not an MMR and does not appear in the MMR memory map. It is accessed through the HVCON registered
interface and data is read back from this register via HVDAT. In response to a high voltage interrupt event, the high
voltage interrupt controller simultaneously and automatically loads the current value of the high voltage status register
(HVSTA) into the HVDAT register.
Table 60. HVSTA Bit Designations
Bit
Description
7 to 3
Reserved. These bits should not be used and are reserved for future use.
2
Low voltage flag status bit. Valid only if enabled via HVCFG[4].
This bit is 0 on power-on if REG_DVDD has dropped below 2.1 V. In this state, RAM contents can be deemed corrupt.
This bit is 1 on power-on if REG_DVDD has not dropped below 2.1 V. In this state, RAM contents can be deemed valid. It
is only cleared by re-enabling the low voltage flag in HVCFG[4].
1
Reserved. This bit should not be used and is reserved for future use.
0
LIN short-circuit status interrupt.
This bit is 0 during normal LIN operation and is cleared automatically by reading the HVSTA register.
This bit is 1 if a LIN short circuit is detected. In this condition, the LIN driver is automatically disabled.
LOW VOLTAGE FLAG (LVF)
The ADuC7039 features a low voltage flag (LVF) that, when
enabled, allows the user to monitor REG_DVDD (see the Low
Voltage Flag (LVF) section). When enabled via HVCFG[4], the
LVF can be monitored through HVSTA[2]. If REG_DVDD drops
below 2.1 V, then HVSTA[2] is cleared and the RAM contents
are corrupted. After the LVF is enabled, it is only reset by
REG_DVDD dropping below 2.1 V or by disabling the LVF
functionality using HVCFG[4].
HANDLING HV INTERFACE INTERRUPT AND HV
COMMUNICATION
HV Interrupt
An interrupt controller is also integrated with the high voltage
circuits. If enabled through IRQEN[10], a LIN short circuit
event can assert the high voltage interrupt signal and interrupt
the MCU core.
Although the normal MCU response to this interrupt event is
to vector to the IRQ or FIQ interrupt vector address, the high
voltage interrupt controller simultaneously and automatically
loads the current value of the high voltage status register
(HVSTA) into the HVDAT register. During this time, the
busy bit in HVCON[0] is set to indicate the transfer is in
progress and clears after 10 s to indicate the HVSTA
contents are available in HVDAT.
The interface should be interrupt driven. The interrupt handler
can, therefore, poll the busy bit in HVCON until it deasserts.
Once the busy bit is cleared, HVCON[1] must be checked to
ensure the data was read correctly. Then the HVDAT register
can be read. At this time, HVDAT holds the value of the
HVSTA register.
Reading the HVSTA register clears the interrupt; therefore,
it is not recommended to read HVSTA at any time.
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