參數(shù)資料
型號(hào)： EVAL-ADUC7039QSPZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 46/92頁(yè)
文件大?。?/td> 0K
描述： BOARD EVAL FOR ADUC7039
設(shè)計(jì)資源： ADuC7039QSPZ Gerber Files
EVAL-ADuC7039 Schematic & Brd Outline
標(biāo)準(zhǔn)包裝： 1
系列： QuickStart™ PLUS 套件
類型： MCU
適用于相關(guān)產(chǎn)品： ADuC7039
所含物品： 板
ADuC7039
Data Sheet
Rev. D | Page 50 of 92
The operating mode and clocking mode are controlled using
two MMRs, PLLCON and POWCON, and the status of the
PLL, PLL lock and PLL interrupt, is indicated by PLLSTA.
It is recommended that before powering down the ADuC7039,
switch the clock source for the PLL to the low power oscillator
to reduce wake-up time. The low power oscillator is always
active.
When the ADuC7039 wakes up from power-down, the MCU
core begins executing code as soon as the PLL begins oscillat-
ing. This occurs before the PLL has locked to a frequency of
20.48 MHz. To ensure the Flash/EE memory controller is execut-
ing with a valid clock, the controller is driven with a PLL output
divide-by-eight clock source while the PLL is locking. When
the PLL locks, the PLL output is switched from the PLL output
divide-by-eight to the locked PLL output.
If user code requires an accurate PLL output, user code must
poll the lock bit (PLLSTA[1]) after wake-up before resuming
normal code execution.
The PLL is locked within 2 ms after waking up.
PLLCON is a protected MMR with two 32-bit keys: PLLKEY0
(prewrite key) and PLLKEY1 (postwrite key).
PLLKEY0 = 0x000000AA
PLLKEY1 = 0x00000055
POWCON is a protected MMR with two 32-bit keys:
POWKEY0 (prewrite key) and POWKEY1 (postwrite key).
POWKEY0 = 0x00000001
POWKEY1 = 0x000000F4
Sequence Example
An example of writing to both MMRs is as follows:
For programming the POWCON MMR:
//Function Prototype
Void PowerDown (void)
PowerDown PROC
LDR
r2, = 0x98765432
; Load random number for multiplication
LDR
r3, = 0x12345678
LDR
r0, = 0xffff0400
;Base address
MOVS
r1,#0x1
;POWKEY0 = 1
STR
r1,[r0,#4]
;Set POWKEY0
MOVS
r1,#0x01
;Set POWCON value to recommended value of 0x01 to ensure a
10 MHz core clock
STR
r1,[r0,#8]
MOVS
r1,#0xf4
STR
r1,[r0,#0xc]
;Set POWKEY1
UMLAL
r1,r3,r2,r0
;longest possible assembly multiplication instruction
BX
lr
;Flush ARM7 pipeline
ENDP
For programming the PLLCON MMR:
PLLKEY0
=
0xAA
//PLLCON key
PLLCON
=
0x1
//Switch to precision oscillator.
PLLKEY1
=
0x55
//PLLCON key
iA1*iA2
//PSEUDOCODE-dummy cycle to prevent Flash/EE access during clock
change
相關(guān)PDF資料
PDF描述
EYM15DRSH CONN EDGECARD 30POS DIP .156 SLD
AIUR-06-102K INDUCTOR POWER 1000UH 10% T/H
V300C3V3C50B2 CONVERTER MOD DC/DC 3.3V 50W
EGM15DRSH CONN EDGECARD 30POS DIP .156 SLD
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