參數(shù)資料
型號(hào)： EVAL-ADUC7039QSPZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 72/92頁(yè)
文件大?。?/td> 0K
描述： BOARD EVAL FOR ADUC7039
設(shè)計(jì)資源： ADuC7039QSPZ Gerber Files
EVAL-ADuC7039 Schematic & Brd Outline
標(biāo)準(zhǔn)包裝： 1
系列： QuickStart™ PLUS 套件
類型： MCU
適用于相關(guān)產(chǎn)品： ADuC7039
所含物品： 板
ADuC7039
Data Sheet
Rev. D | Page 74 of 92
SERIAL PERIPHERAL INTERFACE (SPI)
The ADuC7039 integrates a complete hardware serial peri-
pheral interface (SPI) on-chip. SPI is an industry standard,
synchronous serial interface that allows eight bits of data to
be synchronously transmitted and simultaneously received,
that is, full duplex up to a maximum bit rate of 5.12 Mb.
The SPI port can be configured for master or slave operation
and typically consists of four pins: MISO, MOSI, SCLK, and SS.
MASTER IN, SLAVE OUT (MISO) PIN
The MISO pin is configured as an input line in master mode
and an output line in slave mode. The MISO line on the master
(data in) should be connected to the MISO line in the slave
device (data out). The data is transferred as byte wide (8-bit)
serial data, MSB first.
MASTER OUT, SLAVE IN (MOSI) PIN
The MOSI pin is configured as an output line in master mode
and an input line in slave mode. The MOSI line on the master
(data out) should be connected to the MOSI line in the slave
device (data in). The data is transferred as byte wide (8-bit)
serial data, MSB first.
SERIAL CLOCK I/O (SCLK) PIN
The master serial clock (SCLK) synchronizes the data being
transmitted and received through the MOSI SCLK period.
Therefore, a byte is transmitted/received after eight SCLK
periods. The SCLK pin is configured as an output in master
mode and as an input in slave mode.
In master mode, polarity and phase of the clock are controlled
by the SPICON register, and the bit rate is defined in the SPIDIV
register as follows:
)
1
(
2
MHz
48
.
20
SPIDIV
f
K
SERIALCLOC
+
×
=
The maximum bit rate in master mode is 10.24 Mb. In slave
mode, the SPICON register must be configured with the phase
and polarity of the expected input clock. The slave accepts data
from an external master up to 5.12 Mb.
In both master and slave modes, data is transmitted on one
edge of the SCLK signal and sampled on the other. Therefore,
it is important that the polarity and phase are configured the
same for the master and slave devices.
SLAVE SELECT (SS) PIN
In SPI slave mode, a transfer is initiated by the assertion of SS,
which is an active low input signal. The SPI port then transmits
and receives 8-bit data until the transfer is concluded by deas-
sertion of SS. In slave mode, SS is always an input.
In SPI master mode, the SS is an active low output signal. It
asserts itself automatically at the beginning of a transfer and
deasserts itself upon completion.
SPI MMR INTERFACE
The following MMR registers control the SPI interface: SPISTA,
SPIRX, SPITX, SPIDIV, and SPICON.
SPIRX Register
Name:
SPIRX
Address:
0xFFFF0A04
Default Value:
0x00
Access:
Read only
Function:
This 8-bit MMR is the SPI receive register.
SPITX Register
Name:
SPITX
Address:
0xFFFF0A08
Default Value:
N/A
Access:
Write only
Function:
This 8-bit MMR is the SPI transmit register.
SPIDIV Register
Name:
SPIDIV
Address:
0xFFFF0A0C
Default Value: 0x00
Access:
Read/Write
Function:
This 6-bit MMR is the SPI baud rate selection
register.
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