
Data Sheet
ADuC7039
Rev. D | Page 13 of 92
THEORY OF OPERATION
The ADuC7039 is a complete system solution for battery moni-
toring in 12 V automotive applications. This device integrates
all of the required features to precisely and intelligently monitor,
process, and diagnose 12 V battery parameters including battery
current, voltage, and temperature over a wide range of operat-
ing conditions.
Minimizing external system components, the device is powered
directly from the 12 V battery. An on-chip, low dropout regula-
tor generates the supply voltage for two integrated, 16-bit, Σ-Δ
ADCs. The ADCs precisely measure battery current, voltage,
and temperature to characterize the state of health and charge
of the car battery.
A Flash/EE memory-based ARM7 microcontroller (MCU) is
also integrated on-chip. It is used to both preprocess the acquired
battery variables and to manage communications from the
ADuC7039 to the main electronic control unit (ECU) via a local
interconnect network (LIN) interface that is integrated on-chip.
The MCU can be configured to operate in normal or flexible
power saving modes of operation.
In its normal operating mode, the MCU is clocked indirectly
from an on-chip oscillator via the phase-locked loop (PLL) at
a maximum clock rate of 10.24 MHz. In its power saving oper-
ating modes, the MCU can be totally powered down, waking
up only in response to the wake-up timer, a POR, or a LIN
communication event.
The ADC can be configured to operate in a normal (full power)
mode of operation, interrupting the MCU after various sample
conversion events.
On-chip factory firmware supports in-circuit Flash/EE repro-
gramming via the LIN or JTAG serial interface ports, and
nonintrusive emulation is also supported via the JTAG interface.
These features are incorporated into a low cost QuickStart
development system supporting the ADuC7039.
The ADuC7039 operates directly from the 12 V battery supply
and is fully specified over a temperature range of 40°C to
+115°C. The ADuC7039 is functional, but with degraded
performance, at temperatures from 115°C to 125°C.
OVERVIEW OF THE
ARM7TDMI-S CORE
The ARM7 core is a 32-bit, reduced instruction set computer
(RISC), developed by ARM Ltd. The ARM7TDMI-S is a von
Neumann-based architecture, meaning that it uses a single
32-bit bus for instruction and data. The length of the data
can be 8, 16, or 32 bits, and the length of the instruction word
is either 16 bits or 32 bits, depending on the mode in which
the core is operating.
The ARM7TDMI-S is an ARM7 core with four additional
Table 5. ARM7TDMI-S
Feature
Description
T
Support for the Thumb (16-bit) instruction set
D
Support for debug
M
Enhanced multiplier
I
Includes the EmbeddedICE module to support
embedded system debugging
Thumb Mode (T)
An ARM instruction is 32 bits long. The ARM7TDMI-S proces-
sor supports a second instruction set compressed into 16 bits,
the Thumb instruction set. Faster code execution from 16-bit
memory and greater code density can be achieved by using the
Thumb instruction set, making the ARM7TDMI-S core
particularly suited for embedded applications.
However, the Thumb mode has three limitations.
Relative to ARM, the Thumb code usually requires more
instructions to perform that same task. Therefore, ARM
code is best for maximizing the performance of time-
critical code in most applications.
The Thumb instruction set does not include some
instructions that are needed for exception handling,
so ARM code can be required for exception handling.
When an interrupt occurs, the core vectors to the interrupt
location in memory and executes the code present at that
address. The first command is required to be in ARM code.
Multiplier (M)
The ARM7TDMI-S instruction set includes an enhanced
multiplier, with four extra instructions to perform 32-bit by
32-bit multiplication with a 64-bit result, and 32-bit by 32-bit
multiplication-accumulation (MAC) with a 64-bit result.
EmbeddedICE (I)
The EmbeddedICE module provides integrated on-chip
debug support for the ARM7TDMI-S. The EmbeddedICE
module contains the breakpoint and watchpoint registers
that allow nonintrusive user code debugging. These registers
are controlled through the JTAG test port. When a breakpoint
or watchpoint is encountered, the processor halts and enters
the debug state. Once in a debug state, the processor registers
can be interrogated, as can the Flash/EE, SRAM, and memory
mapped registers.