- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄15530 > EVAL-ADUC7039QSPZ (Analog Devices Inc)BOARD EVAL FOR ADUC7039 PDF資料下載
參數(shù)資料
| 型號： | EVAL-ADUC7039QSPZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 49/92頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL FOR ADUC7039 |
| 設計資源： | ADuC7039QSPZ Gerber Files EVAL-ADuC7039 Schematic & Brd Outline |
| 標準包裝： | 1 |
| 系列： | QuickStart™ PLUS 套件 |
| 類型： | MCU |
| 適用于相關產(chǎn)品： | ADuC7039 |
| 所含物品： | 板 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁當前第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁
Data Sheet
ADuC7039
Rev. D | Page 53 of 92
Table 39. POWCON MMR Bit Designations
Bit
Description
11 to 9
Reserved. These bits should be written as 0.
8
Precision oscillator enable.
This bit is set by the user to enable the precision oscillator.
This bit is cleared by the user to power down the precision oscillator.
7 to 6
Reserved. These bits should be written as 0.
5
PLL power-down. Timer peripherals power down if driven from the PLL output clock. Timers driven from an active clock
source remain active.
This bit is set by default, and set by hardware on a wake-up event.
This bit is cleared to 0 to power down the PLL. The PLL should not be powered down if either the core or peripherals are
enabled: Bit 3, Bit 4, and Bit 5 must be cleared simultaneously.
4
Peripherals power-down. The peripherals that are powered down by this bit are as follows: SRAM, Flash/EE memory and
GPIO interfaces, and SPI port.
This bit is set by default, and/or by hardware, on a wake-up event. Wake-up timer (Timer2) can still be active if driven
from low power oscillator even if this bit is set.
This bit is cleared to power down the peripherals. The peripherals cannot be powered down if the core is enabled: Bit 3
and Bit 4 must be cleared simultaneously. LIN can still respond to wake-up events even if this bit is cleared.
3
Core power-down. If user code powers down the MCU, include a dummy MCU cycle after the power-down command is
written to POWCON.
This bit is set by default, and set by hardware on a wake-up event.
This bit is cleared to power down the ARM core.
2 to 0
Core clock divider (CD) bits.
000 = 20.48 MHz, 48.83 ns.
001 = 10.24 MHz, 97.66 ns (this is the default setting at power-up).
010 = 5.12 MHz, 195.31 ns.
011 = 2.56 MHz, 390.63 ns.
100 = 1.28 MHz, 781.25 ns.
101 = 640 kHz, 1.56 s.
110 = 320 kHz, 3.125 s.
111 = 160 kHz, 6.25 s.
相關PDF資料 |
PDF描述 |
|---|---|
| EYM15DRSH | CONN EDGECARD 30POS DIP .156 SLD |
| AIUR-06-102K | INDUCTOR POWER 1000UH 10% T/H |
| V300C3V3C50B2 | CONVERTER MOD DC/DC 3.3V 50W |
| EGM15DRSH | CONN EDGECARD 30POS DIP .156 SLD |
| EVAL-ADUC7023QSPZ1 | BOARD EVAL FOR ADUC7023 |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| EVAL-ADUC7060QSPZ | 功能描述:KIT DEV QUICK START ADUC7060 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 通用嵌入式開發(fā)板和套件（MCU、DSP、FPGA、CPLD等） 系列:QuickStart™ PLUS 套件 產(chǎn)品培訓模塊:Blackfin® Processor Core Architecture Overview Blackfin® Device Drivers Blackfin® Optimizations for Performance and Power Consumption Blackfin® System Services 特色產(chǎn)品:Blackfin? BF50x Series Processors 標準包裝:1 系列:Blackfin® 類型:DSP 適用于相關產(chǎn)品:ADSP-BF548 所含物品:板，軟件，4x4 鍵盤，光學撥輪，QVGA 觸摸屏 LCD 和 40G 硬盤 配用:ADZS-BFBLUET-EZEXT-ND - EZ-EXTENDER DAUGHTERBOARDADZS-BFLLCD-EZEXT-ND - BOARD EXT LANDSCAP LCD INTERFACE 相關產(chǎn)品:ADSP-BF542BBCZ-4A-ND - IC DSP 16BIT 400MHZ 400CSBGAADSP-BF544MBBCZ-5M-ND - IC DSP 16BIT 533MHZ MDDR 400CBGAADSP-BF542MBBCZ-5M-ND - IC DSP 16BIT 533MHZ MDDR 400CBGAADSP-BF542KBCZ-6A-ND - IC DSP 16BIT 600MHZ 400CSBGAADSP-BF547MBBCZ-5M-ND - IC DSP 16BIT 533MHZ MDDR 400CBGAADSP-BF548BBCZ-5A-ND - IC DSP 16BIT 533MHZ 400CSBGAADSP-BF547BBCZ-5A-ND - IC DSP 16BIT 533MHZ 400CSBGAADSP-BF544BBCZ-5A-ND - IC DSP 16BIT 533MHZ 400CSBGAADSP-BF542BBCZ-5A-ND - IC DSP 16BIT 533MHZ 400CSBGA |
| EVAL-ADUC7060QSPZU1 | 制造商:Analog Devices 功能描述: |
| EVALADUC7060QSPZU2 | 制造商:Analog Devices 功能描述:QUICK START DEVELOPMENT SYSTEM - Boxed Product (Development Kits) |
| EVAL-ADUC7061MKZ | 功能描述:開發(fā)板和工具包 - ARM Quick Start Development System RoHS:否 制造商:Arduino 產(chǎn)品:Development Boards 工具用于評估:ATSAM3X8EA-AU 核心:ARM Cortex M3 接口類型:DAC, ICSP, JTAG, UART, USB 工作電源電壓:3.3 V |
| EVAL-ADUC7061MKZ | 制造商:Analog Devices 功能描述:ADUC7061MKZ EvaluationBoard |
發(fā)布緊急采購，3分鐘左右您將得到回復。