參數(shù)資料
型號(hào)： EVAL-ADUC7039QSPZ
廠商： Analog Devices Inc
文件頁數(shù)： 3/92頁
文件大?。?/td> 0K
描述： BOARD EVAL FOR ADUC7039
設(shè)計(jì)資源： ADuC7039QSPZ Gerber Files
EVAL-ADuC7039 Schematic & Brd Outline
標(biāo)準(zhǔn)包裝： 1
系列： QuickStart™ PLUS 套件
類型： MCU
適用于相關(guān)產(chǎn)品： ADuC7039
所含物品： 板
Data Sheet
ADuC7039
Rev. D | Page 11 of 92
Pin No.
Mnemonic
Type1
Description
21
GPIO_0/SS
I/O
General-Purpose Digital I/O 0, or SPI Interface. By default, this pin is configured as an input. The
pin has an internal, weak, pull-up resistor and, when not in use, can be left unconnected. This
multifunction pin can be configured in one of two states, namely
General-Purpose Digital I/O 0.
SPI interface, slave select input.
22
GPIO_1/SCLK
I/O
General-Purpose Digital I/O 1 or SPI Interface. By default, this pin is configured as an input. The pin has
an internal, weak, pull-up resistor and, when not in use, can be left unconnected. This multifunction
pin can be configured in one of two states, namely
General-Purpose Digital I/O 1.
SPI interface, serial clock input.
23
GPIO_2/MISO
I/O
General-Purpose Digital I/O 2 or SPI Interface. By default, this pin is configured as an input. The pin has
an internal, weak, pull-up resistor and, when not in use, can be left unconnected. This multifunction
pin can be configured in one of two states, namely
General-Purpose Digital I/O 2.
SPI interface, master input/slave output pin.
24
GPIO_3/MOSI
I/O
General-Purpose Digital I/O 3 or SPI Interface. By default, this pin is configured as an input. The pin has
an internal, weak, pull-up resistor and, when not in use, can be left unconnected. This multifunction
pin can be configured in one of two states, namely
General-Purpose Digital I/O 3.
SPI interface, master output/slave input pin.
25
GPIO_4/IRQ1
I/O
General-Purpose I/O 4/External Interrupt Request 1. By default, this pin is configured as an input. The
pin has an internal, weak, pull-up resistor and when not in use, can be left unconnected.
26
NC
No Connect. This pin is not internally connected, but is reserved for possible future use. Therefore,
do not externally connect this pin.
27
VDD
S
Battery Power Supply to On-Chip Regulator.
28
VBAT
I
Battery Voltage Input to Resistor Divider.
29
LIN
I/O
LIN Serial Interface Input/Output Pin.
30
IO_VSS
S
Ground Reference for LIN Pin.
31
VSS
S
Ground Reference. This is the ground reference for the internal voltage regulators.
32
GPIO_5
I/O
General-Purpose I/O 5. By default, this pin is configured as an input. The pin has an internal, weak,
pull-up resistor and when not in use, can be left unconnected.
EPAD
The exposed pad is internally connected to DGND.
1
I = input, O = output, S = supply.
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