- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄15530 > EVAL-ADUC7039QSPZ (Analog Devices Inc)BOARD EVAL FOR ADUC7039 PDF資料下載
參數(shù)資料
| 型號(hào)： | EVAL-ADUC7039QSPZ |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 83/92頁(yè) |
| 文件大小： | 0K |
| 描述： | BOARD EVAL FOR ADUC7039 |
| 設(shè)計(jì)資源： | ADuC7039QSPZ Gerber Files EVAL-ADuC7039 Schematic & Brd Outline |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | QuickStart™ PLUS 套件 |
| 類型： | MCU |
| 適用于相關(guān)產(chǎn)品： | ADuC7039 |
| 所含物品： | 板 |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)當(dāng)前第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)
ADuC7039
Data Sheet
Rev. D | Page 84 of 92
LIN DIAGNOSTIC
The ADuC7039 features a short-circuit protection on the
LIN pin. If a short-circuit condition is detected on the LIN
pin, HVSTA[0] is set. This generates a high voltage interrupt
if enabled in IRQEN[10]. This bit is cleared by re-enabling the
LIN driver using HVCFG[2]. It is possible to disable this feature
through HVCFG[1].
LIN COMMUNICATION
LIN uses frames for data communication. A frame consists of a
header, break, synch, PID issued by the master, and data bytes,
plus checksum generated by a slave as shown in Figure 32. In a
LIN communication, the PID dictates the behavior of the slave:
receive, transmit, or ignore.
Break
The LIN interface of the ADuC7039 automatically detects the
break and sets a flag in the LINSTA register after receiving a
valid break. The minimum length of the break symbol is 11
nominal slave clocks (at 20 kB). The maximum length of a
valid break symbol is programmable and can be configured in
the LINBK MMR. The LIN interface recognizes a valid break
at any time during a LIN communication and flags a collision
(Bit 4 of LINSTA) if the break occurred during an existing
communication.
Synch
The LIN interface automatically detects the synch byte and sets
the baud rate for the subsequent data of the current LIN frame.
This operation is transparent to the user.
PID
The LIN peripheral sees the PID as a data byte. It is available in
the LINDAT MMR. The software must decode the PID. After
reception of the PID stop bit, an interrupt is generated to read
the contents of the LINDAT register before the contents are
overwritten by the next data byte.
Data Bytes
Subsequent data bytes similarly set the interrupt bit to indicate
that a data byte has been received.
In transmit mode, up to 8 data bytes can be transmitted at a
time followed by a checksum.
Checksum
Checksums are automatically calculated as each byte is received
or transmitted with the inverted value being stored in the
LINCS MMR. By default, checksum calculation are per LIN 2.1
specifications, that is, with enhanced checksum calculations
for all frames except the diagnostic frames and reserved frames
where the classic checksum calculation is used. The hardware
automatically recognizes the PID and calculates the checksum
accordingly. There is no requirement for user code to write to
the LINCON register to change the checksum calculation.
To operate in LIN 1.3 mode, user code LIN initialization
routine must set LINCON[7] to 1, to force the hardware in
classic checksum calculation. This register should not be
modified during LIN communication in receive mode.
LIN MMRS
The interface to the LIN block consists of 8 MMRs:
LINCON is a 16-bit control register. This MMR is described
in Table 61. This register should not be accessed during
data reception.
LINDAT is an 8-bit user accessible data register. This
MMR is double-buffered: a shadow register is used to
receive and transmit while user code reads and writes
from/to LINDAT. The LINSTA MMR indicates the
status of the data.
LINSTA is a 16-bit status register. This MMR is described
LINBR is a 19-bit baud rate register. The baud rate is
automatically set by the LIN peripheral and this register
should not be altered by user code. It indicates the number
of core clock ticks during an 8-bit transmission.
LINBK is a 19-bit break timer register controlling the
maximum length of a break symbol to be detected by the
LIN slave interface as valid. The default count is 5500 core
clock ticks. This represents the time taken for 11 bits to be
transmitted at 20 kHz.
LINCS is an 8-bit checksum register. It contains the
inverted result of the current checksum calculation. The
checksum calculation is performed on every byte that is
received or transmitted according to the setting of Bit 4
in LINCON MMR. In transmit mode, the user sets the
bit after the last data to transmit has been written in the
peripheral. The checksum is sent automatically. In receive
mode, the checksum is calculated on receiving each byte,
regardless if this byte is a data byte or the frame checksum.
For example, when receiving a frame with 4 data bytes, the
LINCS MMR contains the expected frame checksum once
the fourth data byte is received. LINCS should contain
0x00 after receiving a correct checksum.
LINLOW is a 19-bit counter clocked at 10 MHz to wake
up the LIN nodes on the bus. The LIN bus is forced low as
long as the LINLOW MMR is greater than 0. For example,
LINLOW = 0x234 generates an 11-bit break at 20 kB.
LINWU is a 19-bit counter clocked by the low power
oscillator. It is used in sleep mode to specify the length
of the low signal that wakes up the device via LIN. For
example, LINWU = 0x13 ignores any breaks of less than
150 s, and the ADuC7039 remains asleep.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| EYM15DRSH | CONN EDGECARD 30POS DIP .156 SLD |
| AIUR-06-102K | INDUCTOR POWER 1000UH 10% T/H |
| V300C3V3C50B2 | CONVERTER MOD DC/DC 3.3V 50W |
| EGM15DRSH | CONN EDGECARD 30POS DIP .156 SLD |
| EVAL-ADUC7023QSPZ1 | BOARD EVAL FOR ADUC7023 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| EVAL-ADUC7060QSPZ | 功能描述:KIT DEV QUICK START ADUC7060 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 通用嵌入式開發(fā)板和套件（MCU、DSP、FPGA、CPLD等） 系列:QuickStart™ PLUS 套件 產(chǎn)品培訓(xùn)模塊:Blackfin® Processor Core Architecture Overview Blackfin® Device Drivers Blackfin® Optimizations for Performance and Power Consumption Blackfin® System Services 特色產(chǎn)品:Blackfin? BF50x Series Processors 標(biāo)準(zhǔn)包裝:1 系列:Blackfin® 類型:DSP 適用于相關(guān)產(chǎn)品:ADSP-BF548 所含物品:板，軟件，4x4 鍵盤，光學(xué)撥輪，QVGA 觸摸屏 LCD 和 40G 硬盤 配用:ADZS-BFBLUET-EZEXT-ND - EZ-EXTENDER DAUGHTERBOARDADZS-BFLLCD-EZEXT-ND - BOARD EXT LANDSCAP LCD INTERFACE 相關(guān)產(chǎn)品:ADSP-BF542BBCZ-4A-ND - IC DSP 16BIT 400MHZ 400CSBGAADSP-BF544MBBCZ-5M-ND - IC DSP 16BIT 533MHZ MDDR 400CBGAADSP-BF542MBBCZ-5M-ND - IC DSP 16BIT 533MHZ MDDR 400CBGAADSP-BF542KBCZ-6A-ND - IC DSP 16BIT 600MHZ 400CSBGAADSP-BF547MBBCZ-5M-ND - IC DSP 16BIT 533MHZ MDDR 400CBGAADSP-BF548BBCZ-5A-ND - IC DSP 16BIT 533MHZ 400CSBGAADSP-BF547BBCZ-5A-ND - IC DSP 16BIT 533MHZ 400CSBGAADSP-BF544BBCZ-5A-ND - IC DSP 16BIT 533MHZ 400CSBGAADSP-BF542BBCZ-5A-ND - IC DSP 16BIT 533MHZ 400CSBGA |
| EVAL-ADUC7060QSPZU1 | 制造商:Analog Devices 功能描述: |
| EVALADUC7060QSPZU2 | 制造商:Analog Devices 功能描述:QUICK START DEVELOPMENT SYSTEM - Boxed Product (Development Kits) |
| EVAL-ADUC7061MKZ | 功能描述:開發(fā)板和工具包 - ARM Quick Start Development System RoHS:否 制造商:Arduino 產(chǎn)品:Development Boards 工具用于評(píng)估:ATSAM3X8EA-AU 核心:ARM Cortex M3 接口類型:DAC, ICSP, JTAG, UART, USB 工作電源電壓:3.3 V |
| EVAL-ADUC7061MKZ | 制造商:Analog Devices 功能描述:ADUC7061MKZ EvaluationBoard |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。