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| 型號： | EVAL-ADUC7039QSPZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 6/92頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL FOR ADUC7039 |
| 設(shè)計資源： | ADuC7039QSPZ Gerber Files EVAL-ADuC7039 Schematic & Brd Outline |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | QuickStart™ PLUS 套件 |
| 類型： | MCU |
| 適用于相關(guān)產(chǎn)品： | ADuC7039 |
| 所含物品： | 板 |
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ADuC7039
Data Sheet
Rev. D | Page 14 of 92
ARM7 Exceptions
The ARM7 supports five types of exceptions, with a privileged
processing mode associated with each type. The five types of
exceptions are as follows:
Normal interrupt or IRQ. This is provided to service
general-purpose interrupt handling of internal and
external events.
Fast interrupt or FIQ. This is provided to service data
transfer or a communication channel with low latency.
FIQ has priority over IRQ.
Memory abort (prefetch and data).
Attempted execution of an undefined instruction.
Software interrupt (SWI) instruction that can be used
to make a call to an operating system.
Typically, the programmer defines interrupts as IRQ, but
for higher priority interrupts, the programmer can define
interrupts as the FIQ type.
The priority of these exceptions and the vector addresses are
listed in Table 6.
Table 6. Exception Priorities and Vector Addresses
Priority
Exception
Address
1
Hardware reset
0x00
2
Memory abort (data)
0x10
3
FIQ
0x1C
4
IRQ
0x18
5
Memory abort (prefetch)
0x0C
6
Software interrupt1
0x08
6
Undefined instruction1
0x04
1 A software interrupt and an undefined instruction exception have the same
priority and are mutually exclusive.
ARM Registers
The ARM7TDMI-S has 16 standard registers. R0 to R12 are
used for data manipulation, R13 is the stack pointer, R14 is the
link register, and R15 is the program counter that indicates the
instruction currently being executed. The link register contains
the address from which the user has branched (if the branch
and link command was used) or the command during which
an exception occurred.
The stack pointer contains the current location of the stack. As
a general rule, on an ARM7TDMI-S, the stack starts at the top
of the available RAM area and descends using the area as
required. A separate stack is defined for each of the exceptions.
The size of each stack is user configurable and is dependent on
the target application. On the ADuC7039, the stack begins at
0x00040FFC and descends. When programming using high
level languages, such as C, it is necessary to ensure that the stack
does not over-flow. This is dependent on the performance of
the compiler that is used.
When an exception occurs, some of the standard registers are
replaced with registers specific to the exception mode. All
exception modes have replacement banked registers for the
stack pointer (R13) and the link register (R14) as represented
in Figure 4. The FIQ mode has more registers (R8 to R12)
supporting faster interrupt processing. With the increased
number of noncritical registers, the interrupt can be processed
without the need to save or restore these registers, thereby
reducing the response time of the interrupt handling process.
More information relative to the programmer’s model and the
ARM7TDMI-S core architecture can be found in ARM7TDMI-S
technical and ARM architecture manuals available directly from
ARM Ltd.
Figure 4. Register Organization
Interrupt Latency
The worst-case latency for an FIQ consists of the longest time
the request can take to pass through the synchronizer, and the
time for the longest instruction to complete (the longest instruc-
tion is an LDM that loads all the registers including the PC),
plus the time for the data abort entry and the time for FIQ
entry. At the end of this time, the ARM7TDMI-S is executing
the instruction at 0x1C (FIQ interrupt vector address). The
maximum total time is 50 processor cycles, or just under 5 μs
in a system using a continuous 10.24 MHz processor clock. The
maximum IRQ latency calculation is similar but must allow for
the fact that FIQ has higher priority and could delay entry into
the IRQ handling routine for an arbitrary length of time. This
time can be reduced to 42 cycles if the LDM command is not
used; some compilers have an option to compile without using
this command. Another option is to run the part in Thumb
mode where this is reduced to 22 cycles.
The minimum latency for FIQ or IRQ interrupts is five cycles.
This consists of the shortest time the request can take through
the synchronizer and the time to enter the exception mode.
Note that the ARM7TDMI-S initially (first instruction) runs
in ARM (32-bit) mode when an exception occurs. The user
can immediately switch from ARM mode to Thumb mode
if required, for example, when executing interrupt service
routines.
USABLE IN USER MODE
SYSTEM MODES ONLY
SPSR_UND
SPSR_IRQ
SPSR_ABT
SPSR_SVC
R8_FIQ
R9_FIQ
R10_FIQ
R11_FIQ
R12_FIQ
R13_FIQ
R14_FIQ
R13_UND
R14_UND
R0
R1
R2
R3
R4
R5
R6
R7
R8
R9
R10
R11
R12
R13
R14
R15 (PC)
R13_IRQ
R14_IRQ
R13_ABT
R14_ABT
R13_SVC
R14_SVC
SPSR_FIQ
CPSR
USER MODE
FIQ
MODE
SVC
MODE
ABORT
MODE
IRQ
MODE
UNDEFINED
MODE
08
463-
004
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