參數(shù)資料
型號： EVAL-ADUC7039QSPZ
廠商： Analog Devices Inc
文件頁數(shù)： 44/92頁
文件大?。?/td> 0K
描述： BOARD EVAL FOR ADUC7039
設(shè)計資源： ADuC7039QSPZ Gerber Files
EVAL-ADuC7039 Schematic & Brd Outline
標準包裝： 1
系列： QuickStart™ PLUS 套件
類型： MCU
適用于相關(guān)產(chǎn)品： ADuC7039
所含物品： 板
Data Sheet
ADuC7039
Rev. D | Page 49 of 92
SYSTEM CLOCKS
The ADuC7039 integrates a flexible clocking system that can
be clocked from one of two integrated on-chip oscillators: a
precision oscillator or a low power oscillator.
Each of the internal oscillators is divided by four to generate a
clock frequency of 32 kHz. The PLL locks onto a multiple (640)
of 32 kHz, supplied by either of the internal oscillators, to
provide a stable 20.48 MHz clock for the system. By default,
the PLL is driven by the low power oscillator.
The core operates at a frequency of 10.24 MHz, by default.
The ADC is driven by the output of the PLL, divided to give
an ADC clock source of 512 kHz. In low power mode, the ADC
clock source is switched from the standard 512 kHz to the low
power 128 kHz oscillator.
Note that the low power oscillator drives both the watchdog
and core wake-up timers through a divide-by-four circuit. A
detailed block diagram of the ADuC7039 clocking system is
shown in Figure 20.
The two integrated oscillators can be calibrated as described in
Figure 20. ADuC7039 System Clock Generation
128kHz
DIV 4
PRECISION
OSCILLATOR
LOW POWER
OSCILLATOR
128kHz
DIV 4
PLLCON
PLL
FLASH
CONTROLLER
32kHz
PLL OUTPUT
20.48MHz
PLL LOCK
1
8
ADCMDE
CLOCK
DIVIDER
CORE
CLOCK
1
2CD
MCU
ADC
CLOCK
ADC
TIMER0
CORE
CLOCK
HIGH ACCURACY
CALIBRATION
COUNTER
PRECISION
OSCILLATOR
TIMER2
WATCHDOG
LOW POWER
OSCILLATOR
TIMER1
WAKE-UP
LOW POWER
OSCILLATOR
CORE
CLOCK
SPI
CORE
CLOCK
PLL
OUTPUT
LOW POWER
CALIBRATION
COUNTER
LOW POWER
OSCILLATOR
LIN
INTERFACE
LOW POWER
OSCILLATOR
CORE
CLOCK
08463-
019
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