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| 型號： | EVAL-ADUC7039QSPZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 43/92頁 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL FOR ADUC7039 |
| 設計資源： | ADuC7039QSPZ Gerber Files EVAL-ADuC7039 Schematic & Brd Outline |
| 標準包裝： | 1 |
| 系列： | QuickStart™ PLUS 套件 |
| 類型： | MCU |
| 適用于相關產(chǎn)品： | ADuC7039 |
| 所含物品： | 板 |
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ADuC7039
Data Sheet
Rev. D | Page 48 of 92
POWER SUPPLY SUPPORT CIRCUITS
The ADuC7039 integrates two on-chip, low dropout (LDO)
regulators that are driven directly from the battery voltage to
generate a 2.6 V internal supply. This 2.6 V supply is then used
as the supply voltage for the ARM7 MCU and peripherals
including the precision analog circuits on-chip.
The digital LDO functions with two external capacitors in
parallel, on REG_DVDD, whereas, the analog LDO functions
with an external capacitor (0.47 μF) on REG_AVDD.
The ESR of the output capacitor affects stability of the LDO
control loop. An ESR of 5 Ω or less for frequencies above 32 kHz
is recommended to ensure the stability of the regulators.
Power-on-reset (POR), and low voltage flag (LVF) functions are
also integrated to ensure safe operation of the MCU as well as
continuous monitoring of the battery power supply. The POR
circuit is designed to operate with a VDD power-on time (0 V
to 12 V), of greater than 100 μs. It is, therefore, recommended
to carefully select external power supply decoupling compo-
nents to ensure that the VDD supply, power-on time, can
always be guaranteed to be greater than 100 μs. The series
resistor and decoupling capacitor combination on VDD should
be chosen to ensure an RC time constant of at least 100 μs, for
example 10 Ω and 10 μF as shown in Figure 33.
As shown in Figure 19, once the supply voltage (on VDD),
reaches a minimum operating voltage of 3 V, a POR signal
keeps the ARM core in reset for 20 ms. This ensures that the
regulated power supply voltage (REG_DVDD) supplied to the
ARM core and associated peripherals, is above the minimum
operational voltage to guarantee full functionality. A POR flag
is set in the RSTSTA MMR to indicate a POR reset event has
occurred.
At voltages below the POR level, an additional low voltage flag
can be enabled (HVCFG[2]). It can be used to indicate that the
contents of the SRAM remain valid after a reset event. The
operation of the low voltage flag is shown in Figure 19. When
enabled, the status of this bit can be monitored via HVSTA[2].
If this bit is set, then the SRAM contents are valid. If this bit is
cleared, then the SRAM contents can be corrupted.
Figure 19. Typical Power-On Cycle
VDD
3V TYP
12V
2.6V
POR TRIP 3.0V TYP
LVF TRIP 2.1V TYP
REG_DVDD
POR_TRIP
RESET (INTERNAL
ACTIVE LOW RESET
SIGNAL)
ENABLE_LVF
20ms TYP
08
46
3-
0
18
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| EVALADUC7060QSPZU2 | 制造商:Analog Devices 功能描述:QUICK START DEVELOPMENT SYSTEM - Boxed Product (Development Kits) |
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