參數資料
型號： EVAL-ADUC7039QSPZ
廠商： Analog Devices Inc
文件頁數： 66/92頁
文件大?。?/td> 0K
描述： BOARD EVAL FOR ADUC7039
設計資源： ADuC7039QSPZ Gerber Files
EVAL-ADuC7039 Schematic & Brd Outline
標準包裝： 1
系列： QuickStart™ PLUS 套件
類型： MCU
適用于相關產品： ADuC7039
所含物品： 板
Data Sheet
ADuC7039
Rev. D | Page 69 of 92
GENERAL-PURPOSE INPUT/OUTPUT
The ADuC7039 features six general-purpose bidirectional
input/output (GPIO) pins. In general, the GPIO pins have
multiple functions that can be configured by user code. By
default, the GPIO pins are configured in GPIO mode. All
GPIO pins have an internal pull-up resistor, a sink capability
of 0.8 mA and a source capability of 0.1 mA. A typical GPIO
structure is shown Figure 28.
Figure 28. ADuC7039 GPIO
The six GPIOs are grouped into one 6-bit wide port. The GPIO
assignment within this port is detailed in Table 49.
During normal operation, user code can control the function
and state of the external GPIO pins by these general-purpose
registers. All GPIO pins retain their external level (high or low)
during power-down (POWCON) mode.
Table 49. External GPIO Pin to Internal Port Signal
Assignments
GPIO
Pin
Port
Signal
Functionality (Defined by GPCON)
GPIO_0
P0.0
General-purpose I/O.
SS
Slave select I/O for SPI.
GPIO_1
P0.1
General-purpose I/O.
SCLK
Serial clock I/O for SPI.
GPIO_2
P0.2
General-purpose I/O.
MISO
Master input, slave output for SPI.
GPIO_3
P0.3
General-purpose I/O.
MOSI
Master output, slave input for SPI.
GPIO_4
P0.4
General-purpose I/O.
LINRx
LIN input for LIN conformance testing.
IRQ1
External Interrupt Request 1.
GPIO_5
P0.5
General-purpose I/O.
LINTx
LIN output for LIN conformance testing.
Port pins are configured and controlled by four MMRs as
follows:
GPCON: control register
GPDAT: configuration and data register
GPSET: data set
GPCLR: data clear
GPIO
REG_DVDD
OUTPUT DRIVE ENABLE
GPDAT[31:24]
OUTPUT DATA
GPDAT[23:16]
INPUT DATA
GPDAT[7:0]
08463-
025
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參數描述
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EVAL-ADUC7061MKZ 制造商:Analog Devices 功能描述:ADUC7061MKZ EvaluationBoard
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