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| 型號(hào)： | EVAL-ADUC7039QSPZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 64/92頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL FOR ADUC7039 |
| 設(shè)計(jì)資源： | ADuC7039QSPZ Gerber Files EVAL-ADuC7039 Schematic & Brd Outline |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | QuickStart™ PLUS 套件 |
| 類型： | MCU |
| 適用于相關(guān)產(chǎn)品： | ADuC7039 |
| 所含物品： | 板 |
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Data Sheet
ADuC7039
Rev. D | Page 67 of 92
TIMER2—WATCHDOG TIMER
Timer2 has two modes of operation: normal mode and watchdog
mode. The watchdog timer is used to recover from an illegal
software state. Once enabled, it requires periodic servicing to
prevent it from forcing a reset of the processor.
Timer2 reloads the value from T2LD when Timer2 overflows
in normal mode, or immediately when T2CLRI is written in
watchdog mode.
Normal Mode
Timer2 in normal mode is identical to Timer0 in 16-bit mode
of operation, except for the clock source and prescaler. The
clock source is the low power oscillator and can be scaled by
a factor of 1, 16, or 256.
Watchdog Mode
Watchdog mode is entered by setting T2CON[5]. Timer2
decrements from the timeout value present in the T2LD
register until 0. The maximum timeout is 524 seconds, using
the maximum prescalar of 1/256 and full scale in T2LD.
User software should not configure a timeout period of less
than 30 ms. This is to avoid any conflict with Flash/EE memory
page erase cycles, which require 20 ms to complete a single page
erase cycle.
If T2VAL reaches 0, a reset or an interrupt occurs, depending
on T2CON[1]. To avoid a reset or an interrupt event, any
value must be written to T2CLRI before T2VAL reaches 0.
This reloads the counter with T2LD and begins a new timeout
period.
Once watchdog mode is entered, T2LD and T2CON are write-
protected.
These two registers cannot be modified until a power-on reset
event resets the watchdog timer. After any other reset event, the
watchdog timer continues to count. The watchdog timer should
be configured in the initial lines of user code to avoid an infinite
loop of watchdog resets.
Timer2 is automatically halted during the JTAG debug access
and recommences counting only once JTAG has relinquished
control of the ARM7 core. By default, Timer2 continues to
count during power-down. This can be disabled by setting
T2CON[0]. It is recommended that the default value be
used, that is, that the watchdog timer continue to count
during power-down.
The Timer2 interface consists of four MMRs.
T2LD is a 16-bit register that holds the 16-bit value that is
loaded into the counter.
T2VAL is a 16-bit register that hold the 16-bit current value
of Timer2.
T2CLRI is an 8-bit register. Writing any value to this
register clears the Timer2 interrupt in normal mode
or resets a new timeout period in watchdog mode.
T2CON is a 16-bit configuration register described
Timer2 Load Registers
Name:
T2LD
Address:
0xFFFF0340
Default Value: 0x0050
Access:
Read/write
Function:
T2LD is a 16-bit register that holds the 16-bit
value that is loaded into the counter.
Timer2 Clear Register
Name:
T2CLRI
Address:
0xFFFF034C
Access:
Write only
Function:
This 8-bit, write-only MMR is written (with
any value) by user code to clear the interrupt,
if in normal mode or to reset the timeout if
in watchdog mode.
Timer2 Value Register
Name:
T2VAL
Address:
0xFFFF0344
Default Value: 0x0050
Access:
Read only
Function:
T2VAL is a 16-bit register that holds the
current value of Timer2.
Timer2 Control Register
Name:
T2CON
Address:
0xFFFF0348
Default Value: 0x0000
Access:
Read/write
Function:
This 16-bit MMR configures the mode of
operation of Timer2.
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