參數(shù)資料
型號： EVAL-ADUC7039QSPZ
廠商： Analog Devices Inc
文件頁數(shù)： 57/92頁
文件大?。?/td> 0K
描述： BOARD EVAL FOR ADUC7039
設(shè)計資源： ADuC7039QSPZ Gerber Files
EVAL-ADuC7039 Schematic & Brd Outline
標(biāo)準包裝： 1
系列： QuickStart™ PLUS 套件
類型： MCU
適用于相關(guān)產(chǎn)品： ADuC7039
所含物品： 板
ADuC7039
Data Sheet
Rev. D | Page 60 of 92
IRQ
The IRQ is the exception signal to enter the IRQ mode of the
processor. It is used to service the general-purpose interrupt
handling of internal and external events.
All 32 bits are logically OR’ed to create a single IRQ signal to the
ARM7TDMI-S core. The four 32-bit registers dedicated to IRQ
follow.
IRQSIG
IRQSIG is a read-only register that reflects the status of the
different IRQ sources. If a peripheral generates an IRQ signal,
the corresponding bit in the IRQSIG is set; otherwise, it is
cleared. The IRQSIG bits are cleared when the interrupt in the
particular peripheral is cleared. All IRQ sources can be masked
in the IRQEN MMR.
IRQEN
IRQEN provides the value of the current enable mask. When
a bit is set to 1, the corresponding source request is enabled
to create an IRQ exception. When a bit is set to 0, the corre-
sponding source request is disabled or masked which does
not create an IRQ exception. The IRQEN register cannot be
used to disable an interrupt.
IRQCLR
IRQCLR is a write-only register that allows the IRQEN register
to clear to mask an interrupt source. Each bit set to 1 clears the
corresponding bit in the IRQEN register without affecting the
remaining bits. The pair of registers, IRQEN
and IRQCLR, allow independent manipulation of the enable
mask without requiring an atomic read-modify-write.
IRQSTA
IRQSTA is a read-only register that provides the current enabled
IRQ source status (effectively a logic AND of the IRQSIG and
IRQEN bits). When set to 1, that source generates an active IRQ
request to the ARM7TDMI-S core. There is no priority encoder
or interrupt vector generation. This function is implemented in
software in a common interrupt handler routine.
Fast Interrupt Request (FIQ)
The fast interrupt request (FIQ) is the exception signal to enter
the FIQ mode of the processor. It is provided to service data
transfer or communication channel tasks with low latency. The
FIQ interface is identical to the IRQ interface and provides the
second level interrupt (highest priority). Four 32-bit registers
are dedicated to FIQ: FIQSIG, FIQEN, FIQCLR, and FIQSTA.
Bit 31 to Bit 1 of FIQSTA are logically OR’ed to create the FIQ
signal to the core and to Bit 0 of both the FIQ and IRQ registers
(FIQ source).
The logic for FIQEN and FIQCLR does not allow an interrupt
source to be enabled in both IRQ and FIQ masks. A bit set to
1 in FIQEN clears, as a side effect, the same bit in IRQEN.
Likewise, a bit set to 1 in IRQEN clears, as a side effect, the
same bit in FIQEN. An interrupt source can be disabled in
both IRQEN and FIQEN masks.
Programmed Interrupts
Because the programmed interrupts are not maskable, they are
controlled by another register, SWICFG that writes into both
IRQSTA and IRQSIG registers and/or the FIQSTA and FIQSIG
registers at the same time.
The 32-bit register dedicated to software interrupt is SWICFG
described in Table 45. This MMR allows the control of a pro-
grammed source interrupt.
Table 45. SWICFG MMR Bit Designations
Bit
Description
31 to 3
Reserved.
2
Programmed interrupt FIQ.
Setting/clearing this bit corresponds to
setting/clearing Bit 1 of FIQSTA and FIQSIG.
1
Programmed interrupt IRQ.
Setting/clearing this bit corresponds to
setting/clearing Bit 1 of IRQSTA and IRQSIG.
0
Reserved.
Note that any interrupt signal must be active for at least
the minimum interrupt latency time, to be detected by the
interrupt controller and to be detected by the user in the
IRQSTA/FIQSTA register.
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