參數(shù)資料
型號(hào)： EVAL-ADUC7039QSPZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 47/92頁(yè)
文件大?。?/td> 0K
描述： BOARD EVAL FOR ADUC7039
設(shè)計(jì)資源： ADuC7039QSPZ Gerber Files
EVAL-ADuC7039 Schematic & Brd Outline
標(biāo)準(zhǔn)包裝： 1
系列： QuickStart™ PLUS 套件
類型： MCU
適用于相關(guān)產(chǎn)品： ADuC7039
所含物品： 板
Data Sheet
ADuC7039
Rev. D | Page 51 of 92
PLLSTA Register
Name:
PLLSTA
Address:
0xFFFF0400
Default Value:
0xXX
Access:
Read only
Function:
This 8-bit register allows user code to monitor the lock state of the PLL.
Table 37. PLLSTA MMR Bit Designations
Bit
Description
7 to 2
Reserved.
1
PLL lock status bit, read only.
This bit is set automatically when the PLL is locked and outputting 20.48 MHz.
This bit is cleared automatically when the PLL is not locked and outputting an fCORE divide-by-8 clock source.
0
PLL interrupt.
Set this bit if the PLL lock status bit signal goes low.
This bit is cleared by user code when writing 1 to this bit.
PLLCON Prewrite Key PLLKEY0
Name:
PLLKEY0
Address:
0xFFFF0410
Access:
Write only
Key:
0x000000AA
Function:
PLLCON is a keyed register that requires a 32-bit key value to be written before and after PLLCON. PLLKEY0 is the
prewrite key.
PLLCON Postwrite Key PLLKEY1
Name:
PLLKEY1
Address:
0xFFFF0418
Access:
Write only
Key:
0x00000055
Function:
PLLCON is a keyed register that requires a 32-bit key value to be written before and after PLLCON. PLLKEY1 is the
postwrite key.
PLLCON Register
Name:
PLLCON
Address:
0xFFFF0414
Default Value: 0x00
Access:
Read/write
Function:
This 8-bit register allows user code to dynamically select the PLL source clock from two different oscillator sources.
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