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| 型號： | EVAL-ADUC7039QSPZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 55/92頁 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL FOR ADUC7039 |
| 設(shè)計資源： | ADuC7039QSPZ Gerber Files EVAL-ADuC7039 Schematic & Brd Outline |
| 標準包裝： | 1 |
| 系列： | QuickStart™ PLUS 套件 |
| 類型： | MCU |
| 適用于相關(guān)產(chǎn)品： | ADuC7039 |
| 所含物品： | 板 |
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Data Sheet
ADuC7039
Rev. D | Page 59 of 92
INTERRUPT SYSTEM
There are 10 interrupt sources on the ADuC7039 that are con-
trolled by the interrupt controller. Most interrupts are generated
from the on-chip peripherals such as the ADC and timers. The
ARM7TDMI-S CPU core only recognizes interrupts as one of
two types: a normal interrupt request (IRQ) and a fast interrupt
request (FIQ). All the interrupts can be masked separately.
The control and configuration of the interrupt system is
managed through nine interrupt-related registers: four
dedicated to IRQ and four dedicated to FIQ. An additional
MMR is used to select the programmed interrupt source.
The bits in each IRQ and FIQ register represent the same
interrupt source as described in Table 44.
IRQSTA/FIQSTA should be saved immediately upon entering
the interrupt service routine (ISR) to ensure that all valid
interrupt sources are serviced.
The interrupt generation to the ARM7TDMI-S core is shown
Consider the example of Timer0, which is configured to
generate a timeout every 5 ms. After the first 5 ms timeout,
FIQSIG/IRQSIG[2] is set and can only be cleared by writing
to T0CLRI. If Timer0 is not enabled in either IRQEN or
FIQEN, then FIQSTA/IRQSTA[2] is not set and an interrupt
does not occur. However, if Timer0 is enabled in either IRQEN
or FIQEN, then either FIQSTA/IRQSTA[2] is set or an interrupt
(either an FIQ or IRQ) occurs.
Figure 22. Interrupt Structure
Note that the IRQ and FIQ interrupt bit definitions in the CPSR
only control interrupt recognition by the ARM core, not by the
peripherals. For example, if Timer2 is configured to generate an
IRQ via IRQEN, the IRQ interrupt bit is set (disabled) in the
CPSR, and the ADuC7039 is powered down. When an interrupt
occurs, the peripherals are woken, but the ARM core remains
powered down. This is equivalent to POWCON = 0x71. The
ARM core can only be powered up by a reset event if this occurs.
Table 44. IRQ/FIQ MMRs Bit Designations
Bit
Description
Comments
0
All interrupts OR’ed
Only available in the FIQ MMRs
1
SWI
Not used in IRQEN/CLR and FIQEN/CLR
2
Timer0
3
Timer1 or wake-up timer
4
Timer2 or watchdog timer
5
LIN
6
Flash/EE interrupt
7
PLL lock
8
ADC
9
SPI
10
High voltage
11
Low power oscillator calibration complete
12
Reserved
13
IRQ1 ( GPIO IRQ1)
External interrupt at GPIO4
14 to 31
Reserved
08463-
021
TIMER0
TIMER1
TIMER2
LIN H/W
FLASH/EE
PLL LOCK
ADC
SPI
HV
TIMER0
TIMER1
TIMER2
LIN H/W
FLASH/EE
PLL LOCK
ADC
SPI
HV
IRQ1
IRQ
FIQ
IR
QS
TA
FIQS
TA
IR
QS
IG
FIQS
IG
IR
QS
IG
FIQE
N
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