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| 型號： | EVAL-ADUC7039QSPZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 73/92頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL FOR ADUC7039 |
| 設(shè)計資源： | ADuC7039QSPZ Gerber Files EVAL-ADuC7039 Schematic & Brd Outline |
| 標準包裝： | 1 |
| 系列： | QuickStart™ PLUS 套件 |
| 類型： | MCU |
| 適用于相關(guān)產(chǎn)品： | ADuC7039 |
| 所含物品： | 板 |
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Data Sheet
ADuC7039
Rev. D | Page 75 of 92
SPI Status Register
Name:
SPISTA
Address:
0xFFFF0A00
Default Value:
0x0000
Access:
Read only
Function:
This 16-bit MMR contains the status of the SPI interface in both master and slave modes.
Table 54. SPISTA MMR Bit Designations
Bit
Description
15 to 12
Reserved bits.
11
SPI Rx FIFO excess bytes present.
This bit is set when there are more bytes in the Rx FIFO than indicated in the SPIRXMDE bits in SPICON.
This bit is cleared when the number of bytes in the FIFO is equal or less than the number in SPIRXMDE.
10 to 8
SPI Rx FIFO status bits.
[000] = Rx FIFO is empty.
[001] = 1 valid byte in the FIFO.
[010] = 2 valid byte in the FIFO.
[011] = 3 valid byte in the FIFO.
[100] = 4 valid byte in the FIFO.
7
SPI Rx FIFO overflow status bit.
This bit is set when the Rx FIFO was already full when new data was loaded to the FIFO. This bit generates an interrupt except
when SPICON[12] is set.
This bit is cleared when the SPISTA register is read.
6
SPI Rx IRQ status bit.
This bit is set when a receive interrupt occurs. This bit is set when SPICON[6] is cleared and the required number of bytes have
been received.
This bit is cleared when the SPISTA register is read.
5
SPI Tx IRQ status bit.
This bit is set when a transmit interrupt occurs. This bit is set when SPICON[6] is set and the required number of bytes have been
transmitted.
This bit is cleared when the SPISTA register is read.
4
SPI Tx FIFO underflow.
This bit is set when a transmit is initiated without any valid data in the Tx FIFO. This bit generates an interrupt except when
SPICON[13] is set.
This bit is cleared when the SPISTA register is read.
3 to 1
SPI Tx FIFO status bits.
000 = Tx FIFO is empty.
001 = 1 valid byte in the FIFO.
010 = 2 valid byte in the FIFO.
011 = 3 valid byte in the FIFO.
100 = 4 valid byte in the FIFO.
0
SPI interrupt status bit.
This bit is set to 1 when an SPI-based interrupt occurs.
This bit is cleared after reading SPISTA.
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