參數(shù)資料
型號： EVAL-ADUC7039QSPZ
廠商： Analog Devices Inc
文件頁數(shù)： 19/92頁
文件大小： 0K
描述： BOARD EVAL FOR ADUC7039
設計資源： ADuC7039QSPZ Gerber Files
EVAL-ADuC7039 Schematic & Brd Outline
標準包裝： 1
系列： QuickStart™ PLUS 套件
類型： MCU
適用于相關(guān)產(chǎn)品： ADuC7039
所含物品： 板
ADuC7039
Data Sheet
Rev. D | Page 26 of 92
MEMORY MAPPED REGISTERS (MMR)
The memory mapped register (MMR) space is mapped into
the top 4 kB of the MCU memory space and accessed by
indirect addressing, load, and store commands through the
ARM7 banked registers. An outline of the memory mapped
register bank for the ADuC7039 is shown in Figure 10.
The MMR space provides an interface between the CPU and
all on-chip peripherals. All registers except the ARM7 core
registers (described in the ARM Registers section) reside in
the MMR area.
As shown in the detailed MMR maps in the Complete MMR
Listing section (Table 14 to Table 23), the MMR data widths
vary from 1 byte (8 bits) to 4 bytes (32 bits). The ARM7 core
can access any of the MMRs (single byte or multiple byte width
registers) with a 32-bit read or write access.
The resultant read, for example, is aligned per little endian
format as previously described in this data sheet. However,
errors result if the ARM7 core tries to access 4-byte (32-bit)
MMRs with a 16-bit access. In the case of a (16-bit) write
access to a 32-bit MMR, the (upper) 16 most significant
bits are written as 0s. More obviously, in the case of a
16-bit read access to a 32-bit MMR, only 16 of the MMR
bits can be read.
Figure 10. Top Level MMR Map
INTERRUPT
CONTROLLER
0xFFFF0110
0xFFFF0000
REMAP AND
SYSTEM CONTROL
0xFFFF0248
0xFFFF0220
TIMER 0
0xFFFF0310
0xFFFF0300
WAKE-UP
TIMER 1
0xFFFF0334
0xFFFF0320
WATCHDOG
TIMER 2
0xFFFF0350
0xFFFF0340
PLL AND
OSCILLATOR CONTROL
0xFFFF04A4
0xFFFF0400
ADC
0xFFFF0560
0xFFFF0500
LIN
HARDWARE
0xFFFF0800
0xFFFF0700
HV
INTERFACE
0xFFFF0810
0xFFFF0804
SPI
0xFFFF0A14
0xFFFF0A00
GPIO
0xFFFF0D20
0xFFFF0D00
FLASH CONTROL
INTERFACE
0xFFFF0E24
0xFFFFFFFF
0xFFFF0E00
08
46
3-
0
11
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