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| 型號： | EVAL-ADUC7039QSPZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 59/92頁 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL FOR ADUC7039 |
| 設(shè)計資源： | ADuC7039QSPZ Gerber Files EVAL-ADuC7039 Schematic & Brd Outline |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | QuickStart™ PLUS 套件 |
| 類型： | MCU |
| 適用于相關(guān)產(chǎn)品： | ADuC7039 |
| 所含物品： | 板 |
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ADuC7039
Data Sheet
Rev. D | Page 62 of 92
Figure 24. Synchronizer for Signals Crossing Clock Domains
As can be seen from Figure 23, the MMR logic and core timer
logic reside in separate and asynchronous clock domains. Any
data coming from the MMR core-clock domain and being
passed to the internal timer domain must be synchronized to
the internal timer clock domain to ensure it is latched correctly
into the core timer clock domain. This is achieved by using two
flip-flops as shown in Figure 24 to not only synchronize but also
to double buffer the data and thereby ensuring data integrity in
the timer clock domain.
As a result of the synchronization block, while timer control
data is latched almost immediately (with the fast, core clock) in
the MMR clock domain, this data in turn will not reach the core
timer logic for at least two periods of the selected internal timer
domain clock.
PROGRAMMING THE TIMERS
Understanding the synchronization across timer domains also
requires the user code to carefully program the timers when
stopping or starting them. The recommended code controls the
timer block when stopping and starting the timers and when
using different clock domains. This can be in particular very
critical if timers are enabled to generate a IRQ or FIQ exception,
An example, using Timer1 follows.
Halting Timer1
When halting Timer1, it is recommended that IRQEN bit for
Timer1 be masked (using IRQCLR). This prevents unwanted
IRQs from generating an interrupt in the MCU before the T1CON
control bits have been latched in the Timer1 internal logic.
IRQCLR = WAKEUP_TIMER_BIT;
// Masking interrupts
T1CON = 0x00;
// halting the timer,
Starting Timer1
When starting Timer1, it is recommended to first load Timer1
with the required TxLD value. Next, start the timer by setting
the T1CON bits as required. This enables the timer but only
once the T1CON bits have been latched internally in the
Timer1 clock domain. Therefore, it is advised that a delay of
more than three clock periods (that is, 100 μs for a 32 kHz timer
clock source) is inserted to allow both the T1LD value and the
T1CON value to be latched through the synchronization logic
and reach the Timer1 domain. After the delay, it is recom-
mended that any (inadvertent) Timer1 interrupts are now
cleared using T1CLRI = 0x00. Finally, the Timer1 system
interrupt can be unmasked by setting the appropriate bit in
the IRQEN MMR. An example of this code follows.
Sequence Example
It is assumed Timer1 is halted as previously described.
T1LD = 0x1;
// Reload timer
T1CON = 0x001F;
// Enable timer, Low power oscillator, 32768 prescaler, periodic
Delay(100us);
// Include delay to ensure T1CON bits take effect
T1CLRI = 0 ;
//* Clear Timer IRQ
IRQEN = WAKEUP_TIMER_BIT;
// Unmask Timer1
TIMER 2 LOW POWER
CLOCK DOMAIN
SYNCHRONIZED SIGNAL
UNSYNCHRONIZED
SIGNAL
CORE CLOCK (FCORE) DOMAIN
SYNCHRONIZER FLIP-FLOPS
TARGET CLOCK
08
46
3-
0
34
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| EVAL-ADUC7060QSPZU1 | 制造商:Analog Devices 功能描述: |
| EVALADUC7060QSPZU2 | 制造商:Analog Devices 功能描述:QUICK START DEVELOPMENT SYSTEM - Boxed Product (Development Kits) |
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