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參數(shù)資料
| 型號(hào)： | XRT86SH221IB |
| 廠商： | EXAR CORP |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| 中文描述： | DATACOM, FRAMER, PBGA388 |
| 封裝： | 27 X 27 MM, PLASTIC, BGA-388 |
| 文件頁(yè)數(shù)： | 8/353頁(yè) |
| 文件大?。?/td> | 2330K |
| 代理商： | XRT86SH221IB |
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XRT86SH221
PRELIMINARY
V
SDH-TO-PDH FRAMER/MAPPER WITH INTEGRATED 21-CHANNEL E1 SH LIU
REV. P1.0.5
T
ABLE
119: R
ECEIVE
STM-0 P
ATH
- B3 B
YTE
E
RROR
C
OUNT
R
EGISTER
3 (B3BECR3 = 0
X
0298) .............................................. 174
T
ABLE
120: R
ECEIVE
STM-0 P
ATH
- B3 B
YTE
E
RROR
C
OUNT
R
EGISTER
2 (B3BECR2 = 0
X
0299) .............................................. 175
T
ABLE
121: R
ECEIVE
STM-0 P
ATH
- B3 B
YTE
E
RROR
C
OUNT
R
EGISTER
1 (B3BECR1 = 0
X
029A) .............................................. 175
T
ABLE
122: R
ECEIVE
STM-0 P
ATH
- B3 B
YTE
E
RROR
C
OUNT
R
EGISTER
0 (B3BECR0 = 0
X
029B) .............................................. 176
T
ABLE
123: R
ECEIVE
STM-0 P
ATH
- REI-P E
VENT
C
OUNT
R
EGISTER
3 (REIPECR3 = 0
X
029C) ................................................. 176
T
ABLE
124: R
ECEIVE
STM-0 P
ATH
- REI-P E
VENT
C
OUNT
R
EGISTER
2 (REIPECR2 = 0
X
029D) ................................................. 177
T
ABLE
125: R
ECEIVE
STM-0 P
ATH
- REI-P E
VENT
C
OUNT
R
EGISTER
1 (REIPECR1 = 0
X
029E) .................................................. 177
T
ABLE
126: R
ECEIVE
STM-0 P
ATH
- REI-P E
VENT
C
OUNT
R
EGISTER
0 (REIPECR0 = 0
X
029F) .................................................. 178
T
ABLE
127: R
ECEIVE
STM-0 P
ATH
- R
ECEIVE
P
ATH
T
RACE
M
ESSAGE
B
UFFER
C
ONTROL
R
EGISTER
(RPTMBCR = 0
X
02A3) ....... 178
T
ABLE
128: R
ECEIVE
STM-0 P
ATH
- P
OINTER
V
ALUE
1 (PV1 = 0
X
02A6) ..................................................................................... 179
T
ABLE
129: R
ECEIVE
STM-0 P
ATH
- P
OINTER
V
ALUE
0 (PV0 = 0
X
02A7) ..................................................................................... 180
T
ABLE
130: R
ECEIVE
STM-0 P
ATH
- R
ECEIVE
A
UTO
AIS - C2 B
YTE
V
ALUE
R
EGISTER
(AISC2VR = 0
X
02B9) .............................. 180
T
ABLE
131: R
ECEIVE
STM-0 P
ATH
- R
ECEIVE
A
UTO
AIS - C2 B
YTE
C
ONTROL
R
EGISTER
(AISC2CR = 0
X
02BA) ......................... 180
T
ABLE
132: R
ECEIVE
STM-0 P
ATH
- AUTO AIS C
ONTROL
R
EGISTER
(AUTOACR = 0
X
02BB) ..................................................... 181
T
ABLE
133: R
ECEIVE
STM-0 P
ATH
- SDH R
ECEIVE
A
UTO
A
LARM
R
EGISTER
(RAAR = 0
X
02C3) .................................................. 183
T
ABLE
134: R
ECEIVE
STM-0 P
ATH
- R
ECEIVE
N
EGATIVE
P
OINTER
A
DJUSTMENT
C
OUNT
R
EGISTER
1 (RNPACR1 = 0
X
02C4) ....... 184
T
ABLE
135: R
ECEIVE
STM-0 P
ATH
- R
ECEIVE
N
EGATIVE
P
OINTER
A
DJUSTMENT
C
OUNT
R
EGISTER
0 (RNPACR0 = 0
X
02C5) ....... 184
T
ABLE
136: R
ECEIVE
STM-0 P
ATH
- R
ECEIVE
P
OSITIVE
P
OINTER
A
DJUSTMENT
C
OUNT
R
EGISTER
1 (RPPACR1 = 0
X
02C6) ........ 185
T
ABLE
137: R
ECEIVE
STM-0 P
ATH
- R
ECEIVE
P
OSITIVE
P
OINTER
A
DJUSTMENT
C
OUNT
R
EGISTER
0 (RPPACR0 = 0
X
02C7) ........ 185
T
ABLE
138: R
ECEIVE
STM-0 P
ATH
- R
ECEIVE
J1 B
YTE
C
APTURE
R
EGISTER
(RJ1BCR = 0
X
02D3) ............................................... 185
T
ABLE
139: R
ECEIVE
STM-0 P
ATH
- R
ECEIVE
B3 B
YTE
C
APTURE
R
EGISTER
(RB3BCR = 0
X
02D7) ............................................. 186
T
ABLE
140: R
ECEIVE
STM-0 P
ATH
- R
ECEIVE
C2 B
YTE
C
APTURE
R
EGISTER
(RC2BCR = 0
X
02DB) ............................................. 186
T
ABLE
141: R
ECEIVE
STM-0 P
ATH
- R
ECEIVE
G1 B
YTE
C
APTURE
R
EGISTER
(RG1BCR = 0
X
02DF) ............................................ 186
T
ABLE
142: R
ECEIVE
STM-0 P
ATH
- R
ECEIVE
F2 B
YTE
C
APTURE
R
EGISTER
(RF2BCR = 0
X
02E3) .............................................. 186
T
ABLE
143: R
ECEIVE
STM-0 P
ATH
- R
ECEIVE
H4 B
YTE
C
APTURE
R
EGISTER
(RH4BCR = 0
X
02E7) ............................................. 187
T
ABLE
144: R
ECEIVE
STM-0 P
ATH
- R
ECEIVE
Z3 B
YTE
C
APTURE
R
EGISTER
(RZ3BCR = 0
X
02EB) .............................................. 187
T
ABLE
145: R
ECEIVE
STM-0 P
ATH
- R
ECEIVE
Z4 (K3) B
YTE
C
APTURE
R
EGISTER
(RZ4BCR = 0
X
02EF) ...................................... 187
T
ABLE
146: R
ECEIVE
STM-0 P
ATH
- R
ECEIVE
Z5 B
YTE
C
APTURE
R
EGISTER
(RZ5BCR = 0
X
02F3) .............................................. 187
6.6 TRANSMIT TRANSPORT OVERHEAD PORT CONTROL REGISTER DESCRIPTIONS ............................. 188
T
ABLE
147: T
RANSMIT
STM-0 S
ECTION
C
ONTROL
R
EGISTER
3 (TSCR3 0
X
0700
H
) ...................................................................... 188
T
ABLE
148: T
RANSMIT
STM-0 S
ECTION
C
ONTROL
R
EGISTER
2 (TSCR2 0
X
0701
H
) ...................................................................... 188
T
ABLE
149: T
RANSMIT
STM-0 S
ECTION
C
ONTROL
R
EGISTER
1 (TSCR1 0
X
0702
H
) ...................................................................... 189
T
ABLE
150: S
OURCE
OF
M0/M1 B
YTE
.......................................................................................................................................... 190
T
ABLE
151: T
RANSMIT
STM-0 S
ECTION
C
ONTROL
R
EGISTER
0 (TSCR0 0
X
0703
H
) ...................................................................... 191
T
ABLE
152: T
RANSMIT
STM-0 S
ECTION
A1 B
YTE
E
RROR
M
ASK
(TSA1EM 0
X
0717
H
) .................................................................. 193
T
ABLE
153: T
RANSMIT
STM-0 S
ECTION
A2 B
YTE
E
RROR
M
ASK
(TSA2EM 0
X
071F
H
) .................................................................. 193
T
ABLE
154: T
RANSMIT
STM-0 S
ECTION
B1 B
YTE
E
RROR
M
ASK
(TSB1EM 0
X
0723
H
) .................................................................. 194
T
ABLE
155: T
RANSMIT
STM-0 S
ECTION
B2 B
YTE
S
ELECT
E
RROR
E
NABLE
(TSB2SEE 0
X
0727
H
) ................................................. 194
T
ABLE
156: T
RANSMIT
STM-0 S
ECTION
B2 B
YTE
E
RROR
M
ASK
(TSB2EM 0
X
072B
H
) .................................................................. 195
T
ABLE
157: T
RANSMIT
STM-0 S
ECTION
K2 B
YTE
V
ALUE
R
EGISTER
(TSK2VR 0
X
072E
H
) ............................................................. 196
T
ABLE
158: T
RANSMIT
STM-0 S
ECTION
K1 B
YTE
V
ALUE
R
EGISTER
(TSK1VR 0
X
072F
H
) ............................................................. 196
T
ABLE
159: T
RANSMIT
STM-0 S
ECTION
MS-RDI C
ONTROL
R
EGISTER
(TSMSRDICR 0
X
0733
H
) .................................................. 197
T
ABLE
160: T
RANSMIT
STM-0 S
ECTION
M0M1 B
YTE
V
ALUE
R
EGISTER
(TSM0M1VR 0
X
0737
H
) .................................................. 198
T
ABLE
161: T
RANSMIT
STM-0 S
ECTION
- S1 B
YTE
V
ALUE
R
EGISTER
(TSS1VR 0
X
073B) ............................................................. 198
T
ABLE
162: T
RANSMIT
STM-0 S
ECTION
- F1 B
YTE
V
ALUE
R
EGISTER
(TSF1VR 0
X
073F) ............................................................ 198
T
ABLE
163: T
RANSMIT
STM-0 S
ECTION
- E1 B
YTE
V
ALUE
R
EGISTER
(TSE1VR 0
X
0743) ............................................................ 199
T
ABLE
164: T
RANSMIT
STM-0 S
ECTION
- E2 B
YTE
V
ALUE
R
EGISTER
(TSE2VR 0
X
0747) ............................................................ 199
T
ABLE
165: T
RANSMIT
STM-0 S
ECTION
- J0 B
YTE
V
ALUE
R
EGISTER
(TSJ0VR 0
X
074B) .............................................................. 199
T
ABLE
166: T
RANSMIT
STM-0 S
ECTION
- T
RANSMITTER
J0 B
YTE
C
ONTROL
R
EGISTER
(TSJ0CR 0
X
074F) ................................... 200
6.7 TRANSMIT PATH OVERHEAD PROCESSOR BLOCK REGISTERS ........................................................... 201
T
ABLE
167: T
RANSMIT
STM-0 P
ATH
C
ONTROL
R
EGISTER
- B
YTE
2 (TPCR2 0
X
0781) .................................................................. 201
T
ABLE
168: T
RANSMIT
STM-0 P
ATH
C
ONTROL
R
EGISTER
- B
YTE
1 (TPCR1 0
X
0782) .................................................................. 202
T
ABLE
169: T
RANSMIT
STM-0 P
ATH
C
ONTROL
R
EGISTER
- B
YTE
0 (TPCR0 0
X
0783) .................................................................. 203
T
ABLE
170: T
RANSMIT
STM-0 P
ATH
J1 B
YTE
V
ALUE
R
EGISTER
(TPJ1VR 0
X
0793) ...................................................................... 205
T
ABLE
171: T
RANSMIT
STM-0 P
ATH
B3 B
YTE
E
RROR
M
ASK
R
EGISTER
(TPB3EM 0
X
0797) ......................................................... 205
T
ABLE
172: T
RANSMIT
STM-0 P
ATH
C2 B
YTE
V
ALUE
R
EGISTER
(TPC2VR 0
X
079B) .................................................................... 205
T
ABLE
173: T
RANSMIT
STM-0 P
ATH
G1 B
YTE
V
ALUE
R
EGISTER
(TPG1VR 0
X
079F) ................................................................... 206
T
ABLE
174: T
RANSMIT
STM-0 P
ATH
F2 B
YTE
V
ALUE
R
EGISTER
(TPF2VR 0
X
07A3) .................................................................... 206
T
ABLE
175: T
RANSMIT
STM-0 P
ATH
H4 B
YTE
V
ALUE
R
EGISTER
(TPH4VR 0
X
07A7) .................................................................... 206
T
ABLE
176: T
RANSMIT
STM-0 P
ATH
Z3 B
YTE
V
ALUE
R
EGISTER
(TPZ3VR 0
X
07AB) .................................................................... 207
T
ABLE
177: T
RANSMIT
STM-0 P
ATH
Z4 B
YTE
V
ALUE
R
EGISTER
(TPZ4VR 0
X
N9AF) .................................................................... 207
T
ABLE
178: T
RANSMIT
STM-0 P
ATH
Z5 B
YTE
V
ALUE
R
EGISTER
(TPZ5VR 0
X
07B3) .................................................................... 207
T
ABLE
179: T
RANSMIT
STM-0 P
ATH
P
OINTER
C
ONTROL
R
EGISTER
(TPPCR 0
X
07B7) ................................................................. 208
T
ABLE
180: T
RANSMIT
STM-0 P
ATH
J1 C
ONTROL
R
EGISTER
(TPJ1CR 0
X
07BB) ......................................................................... 210
T
ABLE
181: T
RANSMIT
STM-0 P
ATH
A
RBITRARY
H1 P
OINTER
R
EGISTER
(TPH1PR 0
X
07BF) ....................................................... 210
T
ABLE
182: T
RANSMIT
STM-0 P
ATH
A
RBITRARY
H2 P
OINTER
R
EGISTER
(TPH2PR 0
X
07C3) ....................................................... 211
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| XRT86SH328 | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| XRT86SH328_07 | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| XRT86SH328IB | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| XRT86VL32_1 | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| XRT86VL32_2 | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XRT86SH221IB-F | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC SDH-TO-PDH, VT/TU INTGR 21 CHNL 2FRAME RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| XRT86SH221OR | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| XRT86SH328 | 制造商:EXAR 制造商全稱:EXAR 功能描述:28-CHANNEL SONET/SDH VT MAPPER REGISTER DESCRIPTION WITH M13 |
| XRT86SH328_07 | 制造商:EXAR 制造商全稱:EXAR 功能描述:28-CHANNEL DS1/E1 FRAMER/LIU WITH DS3 MUX & VT-MAPPER - SONET |
| XRT86SH328_08 | 制造商:EXAR 制造商全稱:EXAR 功能描述:28-CHANNEL SONET/SDH VT MAPPER REGISTER DESCRIPTION WITH M13 |
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