
PRELIMINARY
XRT86SH221
178
REV. P1.0.5
SDH-TO-PDH FRAMER/MAPPER WITH INTEGRATED 21-CHANNEL E1 SH LIU
BIT [7:0] - REI-P Event Count - LSB
This RESET-upon-READ register, along with Receive STM-0 Path - REI-P Error Count Register - Bytes 3 through 1,
function as a 32 bit counter, which is incremented anytime the Receive STM-0 POH Processor block detects a Path -
Remote Error Indicator event within the incoming STM-0 SPE data-stream.
N
OTES
:
1.
If the Receive STM-0 POH Processor block is configured to count REI-P events on a per-bit basis, then it
will increment this 32 bit counter by the nibble-value within the REI-P field of the incoming G1 byte.
2.
If the Receive STM-0 POH Processor block is configured to count REI-P events on a per-frame basis,
then it will increment this 32 bit counter each time that it receives an STM-0 SPE that contains a non-zero
REI-P value.
BIT [7:6] - Unused
BIT 5 - New Message Ready
This READ/WRITE bit-field indicates whether or not the Receive Path Trace Message buffer has received a new
expected value.
0 - Indicates NO new expected value has been downloaded into the receive J1 trace buffer.
1 - Indicates a new expected value has been downloaded into the receive J1 trace buffer and can be used to make
comparisons with the accepted J1 message.
BIT 4 - Receive Section Trace Message Buffer Read Selection
This READ/WRITE bit-field is used to specify which of the following Receive Path Trace Message buffer segments to
read.
a. The Actual Receive Path Trace Message Buffer. The Actual Receive Path Trace Message Buffer contains the
contents of the most recently received (and accepted) Path Trace Message via the incoming STM-0 data-stream.
b. The Expected Receive Path Trace Message Buffer. The Expected Receive Path Trace Message Buffer contains
the contents of the Path Trace Message that the user expects to receive. The contents of this particular buffer are
usually specified by the user.
0 - Executing a READ to the Receive J1 Trace Buffer, will return contents within the Valid Message buffer.
1 - Executing a READ to the Receive J1 Trace Buffer, will return contents within the Expected Message Buffer.
N
OTE
:
In the case of the Receive STM-0 POH Processor block, the Receive J1 Trace Buffer is located at Address
Location 0x0500 through 0x053F.
T
ABLE
126: R
ECEIVE
STM-0 P
ATH
- REI-P E
VENT
C
OUNT
R
EGISTER
0 (REIPECR0 = 0
X
029F)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
REI-P_Event_Count[7:0]
RUR
RUR
RUR
RUR
RUR
RUR
RUR
RUR
0
0
0
0
0
0
0
0
T
ABLE
127: R
ECEIVE
STM-0 P
ATH
- R
ECEIVE
P
ATH
T
RACE
M
ESSAGE
B
UFFER
C
ONTROL
R
EGISTER
(RPTMBCR =
0
X
02A3)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Unused
New Message
Ready
Receive
Path Trace
Message
Buffer Read
Select
Receive
Path Trace
Message
Accept
Threshold
Path Trace
Message
Alignment
Type
Receive Path Trace
Message Length[1:0]
R/O
R/O
R/O
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0