
PRELIMINARY
XRT86SH221
214
REV. P1.0.5
SDH-TO-PDH FRAMER/MAPPER WITH INTEGRATED 21-CHANNEL E1 SH LIU
BIT [7:5] - AU-LOP (Administrative Unit - Loss of Pointer) - HP-RDI Code
These three READ/WRITE bit-fields are used to specify the value that the Transmit STM-0 POH Processor Block will
transmit, within the HP-RDI bit-fields of the G1 byte (within the outbound VC-3), whenever the corresponding Receive
STM-0 POH Processor Block detects and declares a AU-LOP condition.
To enable this feature, the user must set BIT 4 (HP-RDI upon AU-LOP) within this register to 1.
BIT 4 - Transmit HP-RDI upon AU-LOP
This READ/WRITE bit-field is used to configure the Transmit STM-0 POH Processor Block to automatically transmit the
HP-RDI Code (as configured in Bits 7 through 5 - within this register) whenever the corresponding Receive STM-0 POH
Processor Block declares a AU-LOP condition
0 - Disables the automatic transmission of HP-RDI upon detection of AU-LOP.
1 - Enables the automatic transmission of HP-RDI upon detection of AU-LOP.
BIT[3:1]AU-AIS (Administrative Unit - Alarm Indication Signal) - HP-RDI Code
These three READ/WRITE bit-fields are used to specify the value that the Transmit STM-0 POH Processor Block will
transmit, within the HP-RDI bit-fields of the G1 byte (within the outbound VC-3), whenever the corresponding Receive
STM-0 POH Processor Block detects and declares an AU-AIS condition.
To enable this feature, the user must set BIT 4 (HP-RDI upon AU-AIS) within this register to 1.
BIT 0 - Transmit HP-RDI upon AU-AIS
This READ/WRITE bit-field is used to configure the Transmit STM-0 POH Processor Block to automatically transmit the
HP-RDI Code (as configured in Bits 7 through 5 - within this register) whenever the corresponding Receive STM-0 POH
Processor Block declares a AU-AIS condition.
0 - Disables the automatic transmission of HP-RDI upon detection of AU-AIS.
1 - Enables the automatic transmission of HP-RDI upon detection of AU-AIS.
BIT [7:4] - Unused
BIT 3:0] - TxPOHClk Output Clock Signal Speed
These READ/WRITE bit-fields are used to specify the frequency of the TxPOHClk output clock signal. The formula that
relates the contents of these register bits to the TxPOHClk frequency is presented below.
FREQ = 51.84 /[2 * (TxPOH_CLOCK_SPEED + 1)
For STM-1 applications, the frequency of the RxPOHClk output signal must be in the range of 2.36MHz to 25.92MHz
T
ABLE
187: T
RANSMIT
STM-0 P
ATH
HP-RDI C
ONTROL
R
EGISTER
- B
YTE
0 (TPHP-RDICR0 0
X
07CB)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
AU-LOP
HP-RDI Code[2:0]
Transmit
HP-RDI
upon
AU-LOP
AU-AIS
HP-RDI Code[2:0]
Transmit
HP-RDI
upon
AU-AIS
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
T
ABLE
188: T
RANSMIT
STM-0 P
ATH
S
ERIAL
P
ORT
C
ONTROL
R
EGISTER
(TPSPCR 0
X
07CF)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Unused
TxPOH Clock Speed[4:0]
R/O
R/O
R/O
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0