
XRT86SH221
PRELIMINARY
161
SDH-TO-PDH FRAMER/MAPPER WITH INTEGRATED 21-CHANNEL E1 SH LIU
REV. P1.0.5
Processor block has received 3 (or 5) consecutive SPEs that each contains the same C2 byte value.Note:Receiving a
given C2 byte value in 3 (or 5) consecutive SPEs also sets this bit-field to 0.
0 - Indicates that the Receive STM-0 POH Processor block is currently NOT declaring the C2 (Path Signal Label Byte)
Unstable defect condition.
1 - Indicates that the Receive STM-0 POH Processor block is currently declaring the C2 (Path Signal Label Byte)
Unstable defect condition.
BIT 5 - Path - Unequipped (UNEQ-P) Defect Declared
This READ-ONLY bit-field indicates whether or not the Receive STM-0 POH Processor block is currently declaring the
UNEQ-P defect condition. The Receive STM-0 POH Processor block will declare the UNEQ-P defect condition, anytime
that it receives at least five (5) consecutive STM-0 frames, in which the C2 byte was set to the value 0x00 (which
indicates that the SPE is Unequipped).
The Receive STM-0 POH Processor block will clear the UNEQ-P defect condition, if it receives at least five (5)
consecutive STM-0 frames, in which the C2 byte was set to a value other than 0x00.
0 - Indicates that the Receive STM-0 POH Processor block is currently NOT declaring the UNEQ-P defect condition.
1 - Indicates that the Receive STM-0 POH Processor block is currently declaring the UNEQ-P defect condition.
N
OTE
:
:The Receive STM-0 POH Processor block will not declare the UNEQ-P defect condition if it configured to
expect to receive STM-0 frames with C2 bytes being set to 0x00 (e.g., if the Receive STM-0 Path - Expected
Path Label Value Register -Address Location= 0x0297) is set to 0x00.
BIT 4 - Path Payload Mismatch (PLM-P) Defect Declared
This READ-ONLY bit-field indicates whether or not the Receive STM-0 POH Processor block is currently declaring the
PLM-P defect condition.The Receive STM-0 POH Processor block will declare the PLM-P defect condition, if it receives
at least five (5) consecutive STM-0 frames, in which the C2 byte was set to a value other than that which it is expecting
to receive. Whenever the Receive STM-0 POH Processor block is determining whether or not it should declare the
PLM-P defect, it will check the contents of the following two registers.
The Receive STM-0 Path - Received Path Label Value Register (Address Location= 0xN196).
The Receive STM-0 Path - Expected Path Label Value Register (Address Location= 0xN197).
The Receive STM-0 Path - Expected Path Label Value Register contains the value of the C2 bytes, that the Receive
STM-0 POH Processor blocks expects to receive.The Receive STM-0 Path - Received Path Label Value Register
contains the value of the C2 byte, that the Receive STM-0 POH Processor block has most received validated (by
receiving this same C2 byte in five consecutive STM-0 frames). The Receive STM-0 POH Processor block will declare
the PLM-P defect condition if the contents of these two register do not match. The Receive STM-0 POH Processor
block will clear the PLM-P defect condition if whenever the contents of these two registers do match.
0 - Indicates that the Receive STM-0 POH Processor block is currently NOT declaring the PLM-P defect condition.
1 - Indicates that the Receive STM-0 POH Processor block is currently declaring the PLM-P defect condition
N
OTE
:
The Receive STM-0 POH Processor block will clear the PLM-P defect, upon declaring the UNEQ-P defect
condition.
BIT 3 - Path Remote Defect Indicator (RDI-P) Defect Declared
This READ-ONLY bit-field indicates whether or not the Receive STM-0 POH Processor block is currently declaring the
RDI-P defect condition.
If the Receive STM-0 POH Processor block is configured to support the Single-bit RDI-P function, then it will declare
the RDI-P defect condition if BIT 5 (within the G1 byte of the incoming STM-0 frame) is set to 1 for RDI-P_THRD number
of incoming consecutive STM-0 frames.
If the Receive STM-0 POH Processor block is configured to support the Enhanced RDI-P (ERDI-P) function, then it will
declare the RDI-P defect condition if Bits 5, 6 and 7 (within the G1 byte of the incoming STM-0 frame) are set to [0, 1,
0], [1, 0, 1] or [1, 1, 0] for RDI-P_THRD number of consecutive STM-0 frames.
0 - Indicates that the Receive STM-0 POH Processor block is NOT currently declaring the RDI-P defect condition.
1 - Indicates that the Receive STM-0 POH Processor block is currently declaring the RDI-P defect condition.
N
OTE
:
The user can specify the value for RDI-P_THRD by writing the appropriate data into Bits 3 through 0 (RDI-P
THRD) within the Receive STM-0 Path - SDH Receive RDI-P Register (Address Location= 0x0293).
BIT 2 - RDI-P (Path - Remote Defect Indicator) Unstable Defect Declared
This READ-ONLY bit-field indicates whether or not the Receive STM-0 POH Processor block is currently declaring the