參數(shù)資料
型號(hào)： XRT86SH221IB
廠商： EXAR CORP
元件分類： 數(shù)字傳輸電路
英文描述： Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
中文描述： DATACOM, FRAMER, PBGA388
封裝： 27 X 27 MM, PLASTIC, BGA-388
文件頁(yè)數(shù)： 6/353頁(yè)
文件大小： 2330K
代理商： XRT86SH221IB
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XRT86SH221
PRELIMINARY
III
SDH-TO-PDH FRAMER/MAPPER WITH INTEGRATED 21-CHANNEL E1 SH LIU
REV. P1.0.5
F
IGURE
47. TAOS (T
RANSMIT
A
LL
O
NES
)...................................................................................................................................... 99
5.1.3 ATAOS (AUTOMATIC TRANSMIT ALL ONES)........................................................................................................... 99
F
IGURE
48. S
IMPLIFIED
B
LOCK
D
IAGRAM
OF
THE
ATAOS F
UNCTION
............................................................................................... 99
5.1.4 QRSS/PRBS GENERATION....................................................................................................................................... 100
5.1.5 TRANSMIT PULSE SHAPER AND FILTER............................................................................................................... 100
5.1.6 DMO (DIGITAL MONITOR OUTPUT)......................................................................................................................... 100
5.2 LINE TERMINATION (TTIP/TRING)................................................................................................................ 100
F
IGURE
49. T
YPICAL
C
ONNECTION
D
IAGRAM
U
SING
I
NTERNAL
T
ERMINATION
................................................................................. 100
5.3 RECEIVE PATH LINE INTERFACE ................................................................................................................ 101
F
IGURE
50. S
IMPLIFIED
B
LOCK
D
IAGRAM
OF
THE
R
ECEIVE
P
ATH
.................................................................................................. 101
5.3.1 LINE TERMINATION (RTIP/RRING)........................................................................................................................... 101
F
IGURE
51. T
YPICAL
C
ONNECTION
D
IAGRAM
U
SING
I
NTERNAL
T
ERMINATION
................................................................................ 101
5.3.2 CLOCK AND DATA RECOVERY .............................................................................................................................. 102
F
IGURE
52. R
ECOVERED
L
INE
C
LOCK
PLL T
IMING
........................................................................................................................ 102
5.3.3 RECOVERED LINE CLOCK OUTPUTS..................................................................................................................... 102
F
IGURE
53. REF_REC[1:0] R
ECOVERED
L
INE
C
LOCK
S
ELECTION
TO
O
UTPUT
P
INS
..................................................................... 102
5.3.4 RLOS (RECEIVER LOSS OF SIGNAL)...................................................................................................................... 103
5.3.5 EXLOS (EXTENDED LOSS OF SIGNAL) .................................................................................................................. 103
5.3.6 JITTER ATTENUATOR............................................................................................................................................... 103
5.3.7 RXMUTE (RECEIVER LOS WITH DATA MUTING) ................................................................................................... 103
F
IGURE
54. S
IMPLIFIED
B
LOCK
D
IAGRAM
OF
THE
R
X
MUTE F
UNCTION
.......................................................................................... 103
6.0 MEMORY AND REGISTER MAP......................................................................................................... 104
6.1 MEMORY MAPPED I/O ADDRESSING .......................................................................................................... 104
T
ABLE
15: C
HANNEL
M
APPING
S
CHEME
....................................................................................................................................... 104
6.2 OVERVIEW OF CONTROL REGISTERS........................................................................................................ 104
T
ABLE
16: M
EMORY
M
AP
- E1 F
RAMERS
...................................................................................................................................... 104
6.3 SDH OPERATION CONTROL REGISTER DESCRIPTIONS.......................................................................... 105
T
ABLE
17: I
NTERRUPT
T
YPE
S
ELECT
(ITS 0
X
0001
H
) ................................................................................................................... 105
T
ABLE
18: R
ECEIVE
STM C
LOCK
D
ETECT
(RSTMCD 0
X
0003
H
) ................................................................................................. 105
T
ABLE
19: D
EVICE
ID R
EGISTER
(DEVID 0
X
0004
H
) .................................................................................................................... 106
T
ABLE
20: R
EVISION
ID R
EGISTER
(REVID 0
X
0005
H
) ................................................................................................................. 106
T
ABLE
21: T
ELECOM
B
US
P
ARITY
E
NABLE
(TBPE 0
X
000B
H
) ....................................................................................................... 106
T
ABLE
22: T
ELECOM
B
US
P
ARITY
E
RROR
E
NABLE
(TBPEE 0
X
000F
H
) ......................................................................................... 107
T
ABLE
23: O
PERATION
B
LOCK
I
NTERRUPT
R
EGISTER
1 (OPIR1 0
X
0012
H
) ................................................................................... 107
T
ABLE
24: O
PERATION
B
LOCK
I
NTERRUPT
R
EGISTER
B
YTE
0 (OPIR0 0
X
0013
H
) .......................................................................... 108
T
ABLE
25: O
PERATION
B
LOCK
I
NTERRUPT
E
NABLE
R
EGISTER
B
YTE
1 (OPIER1 0
X
0016
H
) ........................................................... 109
T
ABLE
26: O
PERATION
B
LOCK
I
NTERRUPT
E
NABLE
R
EGISTER
B
YTE
0 (OPIER0 0
X
0017
H
) ........................................................... 110
T
ABLE
27: D
E
-S
YNC
AND
AU3 M
APPING
C
ONTROL
(DSAU3MC 0
X
001B
H
) .................................................................................. 110
T
ABLE
28: SDH L
OOP
B
ACK
S
ELECT
(SDHLBS 0
X
001F
H
) .......................................................................................................... 111
T
ABLE
29: H
IGH
B
YTE
F
RAME
B
OUNDARY
L
ATENCY
(HBFBL 0
X
0034
H
) ........................................................................................ 111
T
ABLE
30: L
OW
B
YTE
F
RAME
B
OUNDARY
L
ATENCY
(LBFBL 0
X
0035
H
) ......................................................................................... 111
T
ABLE
31: T
ELECOM
B
US
C
ONTROL
1 (TBC1 0
X
0036
H
) .............................................................................................................. 112
T
ABLE
32: T
ELECOM
B
US
C
ONTROL
0 (TBC0 0
X
0037
H
) .............................................................................................................. 113
T
ABLE
33: G
ENERAL
P
URPOSE
I
NPUT
/O
UTPUT
(GPIO 0
X
0047
H
) .................................................................................................. 114
T
ABLE
34: G
ENERAL
P
URPOSE
I
NPUT
/O
UTPUT
D
IRECTION
(GPIOD 0
X
004B
H
) ............................................................................. 114
T
ABLE
35: R
ECOVERED
L
INE
C
LOCK
R
EFERENCE
1 (RLCR1 0
X
004D
H
) ....................................................................................... 114
T
ABLE
36: R
ECOVERED
L
INE
C
LOCK
R
EFERENCE
0 (RLCR0 0
X
004E
H
) ....................................................................................... 114
T
ABLE
37: R
ECOVERED
L
INE
C
LOCK
S
ELECT
FOR
RCLK_REC1
AND
RCLK_REC0 H
ARDWARE
P
INS
.......................................... 115
T
ABLE
38: C
HANNEL
I
NTERRUPT
I
NDICATION
R
EGISTER
11 (CHIIR11 0
X
0054
H
) ........................................................................... 116
T
ABLE
39: C
HANNEL
I
NTERRUPT
I
NDICATION
R
EGISTER
10 (CHIIR10 0
X
0055
H
) ........................................................................... 116
T
ABLE
40: C
HANNEL
I
NTERRUPT
I
NDICATION
R
EGISTER
9 (CHIIR9 0
X
0056
H
) ............................................................................... 116
T
ABLE
41: C
HANNEL
I
NTERRUPT
I
NDICATION
R
EGISTER
8 (CHIIR8 0
X
0057
H
) ............................................................................... 116
T
ABLE
42: C
HANNEL
I
NTERRUPT
I
NDICATION
R
EGISTER
7 (CHIIR7 0
X
0058
H
) ............................................................................... 117
T
ABLE
43: C
HANNEL
I
NTERRUPT
I
NDICATION
R
EGISTER
6 (CHIIR6 0
X
0059
H
) ............................................................................... 117
T
ABLE
44: C
HANNEL
I
NTERRUPT
I
NDICATION
R
EGISTER
5 (CHIIR5 0
X
005A
H
) ............................................................................... 117
T
ABLE
45: C
HANNEL
I
NTERRUPT
I
NDICATION
R
EGISTER
4 (CHIIR4 0
X
005B
H
) ............................................................................... 117
T
ABLE
46: C
HANNEL
I
NTERRUPT
I
NDICATION
R
EGISTER
3 (CHIIR3 0
X
005C
H
) ............................................................................... 118
T
ABLE
47: C
HANNEL
I
NTERRUPT
I
NDICATION
R
EGISTER
2 (CHIIR2 0
X
005D
H
) ............................................................................... 118
T
ABLE
48: C
HANNEL
I
NTERRUPT
I
NDICATION
R
EGISTER
1 (CHIIR1 0
X
005E
H
) ............................................................................... 118
T
ABLE
49: C
HANNEL
I
NTERRUPT
I
NDICATION
R
EGISTER
0 (CHIIR0 0
X
005F
H
) ............................................................................... 118
6.4 RECEIVE TRANSPORT OVERHEAD OPERATION CONTROL REGISTER DESCRIPTIONS..................... 119
T
ABLE
50: R
ECEIVE
STM-0/STM-1 T
RANSPORT
C
ONTROL
R
EGISTER
1 (RTCR1 = 0
X
0202) ........................................................ 119
T
ABLE
51: R
ECEIVE
STM-0/STM-1 T
RANSPORT
C
ONTROL
R
EGISTER
0 (RTCR0 = 0
X
0203) ....................................................... 119
T
ABLE
52: R
ECEIVE
STM-0/STM-1 T
RANSPORT
S
TATUS
R
EGISTER
1 (RTSR1 = 0
X
0206) ........................................................... 121
T
ABLE
53: R
ECEIVE
STM-0/STM-1 T
RANSPORT
S
TATUS
R
EGISTER
0 (RTSR0 = 0
X
0207) .......................................................... 122
T
ABLE
54: R
ECEIVE
STM-0/STM-1 T
RANSPORT
I
NTERRUPT
S
TATUS
R
EGISTER
2 (RTISR2 = 0
X
0209) ........................................ 124
相關(guān)PDF資料
PDF描述
XRT86SH328 Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
XRT86SH328_07 Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
XRT86SH328IB Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
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XRT86VL32_2 Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
XRT86SH221IB-F 功能描述:網(wǎng)絡(luò)控制器與處理器 IC SDH-TO-PDH, VT/TU INTGR 21 CHNL 2FRAME RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
XRT86SH221OR 功能描述:網(wǎng)絡(luò)控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
XRT86SH328 制造商:EXAR 制造商全稱:EXAR 功能描述:28-CHANNEL SONET/SDH VT MAPPER REGISTER DESCRIPTION WITH M13
XRT86SH328_07 制造商:EXAR 制造商全稱:EXAR 功能描述:28-CHANNEL DS1/E1 FRAMER/LIU WITH DS3 MUX & VT-MAPPER - SONET
XRT86SH328_08 制造商:EXAR 制造商全稱:EXAR 功能描述:28-CHANNEL SONET/SDH VT MAPPER REGISTER DESCRIPTION WITH M13
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