
XRT86SH221
PRELIMINARY
69
SDH-TO-PDH FRAMER/MAPPER WITH INTEGRATED 21-CHANNEL E1 SH LIU
REV. P1.0.5
transmit Telecom Bus Alarm output (TxA_Alarm) is generated to tell the external device to generate AIS-P in
the STM-0/STM-1 for which the alarm occurs.
4.9.2
2kHz Mode in STM-1
To align the V1 bytes with H4 in STM-1, the part must be configured for 2kHz. With a 2kHz frame pulse applied
to each of the Voyager Lite devices, the parts can align VT Superframe boundaries. This will allow V1 bytes
within each device to match one another. The TxD_C1J1V1_FP will pulse "High" for all C1J1 bytes. However,
it will only pulse "High" during the V1 byte. V2, V3, and V4 will not be indicated by the external frame pulse.
4.9.3
RECEIVE TELECOM BUS
The receive Telecom Bus interface consists of the following inputs: 8-bit data bus RxD_D[7:0], clock
(RxD_CLK), SPE indication (RxD_PL), C1J1 indication (RxD_C1J1V1_FP), parity (RxD_DP), and a alarm
indication (RxD_ALARM). All of the receive Telecom Bus ports operate at 19.44/6.28 MHz.
The subsections below summarize the functionality of the receive Telecom Bus interface signals. The receive
Telecom Bus clock input RxD_CLK is used to clock in the receive Telecom Bus input signals from an external
device. The clock edge on which the Telecom Bus signals are clocked is programmable via the CKINV control
bits.
Figure 26
shows the functional relationship of the receive Telecom Bus signals.
Each receive Telecom Bus port has an 8-bit wide data bus that inputs the STM-0/STM-1 data from an external
device. The receive Telecom Bus data is byte-aligned and the entire payload, including SDH OH and POH, is
passed in the device. The receive Telecom Bus C1J1 input (RxD_C1J1V1_FP) can be provisioned to provide
two different types of indications, depending on the register setting. When CPOS is set to "1", the
corresponding RxD_C1J1V1_FP signal provides two pulses.
For all sub-frames, the receive Telecom Bus PL input (RxD_PL) is "Low" during the SDH OH bytes in the
RxD_D[7:0] stream and is "High" during the SPE bytes. This includes cases where pointer adjustments are
performed and the SPE needs to be adjusted about the H3 bytes. For example, the H3 bytes are payload bytes
during the frame in which a pointer decrement occurs, therefore the RxD_PL signal will be "High" coincident
with the H3 bytes for that frame. Also in the frame where a pointer increment occurs, the three bytes after the
H3 bytes become stuff, therefore the RxD_PL signal will be "Low" for those bytes. The parity checking can be
configured through the use of the control bits in the interface control registers.
F
IGURE
25. C1J1V1 P
ULSE
IN
STM-1 2
K
H
Z
M
ODE
F
IGURE
26. R
ECEIVE
T
ELECOM
B
US
I
NTERFACE
T
IMING
2kHz FP
C1 J1
C1 J1
C1 J1
C1 J1 V1
C1 J1 V1
TxD_C1J1V1_FP