
XRT86SH221
PRELIMINARY
203
SDH-TO-PDH FRAMER/MAPPER WITH INTEGRATED 21-CHANNEL E1 SH LIU
REV. P1.0.5
BIT 7 - F2 Insertion Type
This READ/WRITE bit-field is used to configure the Transmit STM-0 POH Processor Block to use either the Transmit
STM-0 Path - Transmit F2 Value Register or the TPOH input pin as the source for the F2 byte, in the outbound VC-3.
0 - Configures the Transmit STM-0 POH Processor Block to use the Transmit STM-0 Path - Transmit F2 Value
Register (Address Location= 0x07A3).
1 - Configures the Transmit STM-0 POH Processor Block to use the TPOH input as the source for the F2 byte, in the
outbound VC-3.
BIT [6:5] - High Order Path Remote Error Indication (HP-REI) Insertion Type[1:0]
These two READ/WRITE bit-fields are used to configure the Transmit STM-0 POH Processor Block to use one of the
three following sources for the HP-REI bit-fields (e.g., Bit-7 through -4, within the G1 byte of the outbound VC-3).
From the corresponding Receive STM-0 POH Processor Block (e g., when it detects B3 bytes in its incoming
VC-3 data).
From the Transmit G1 Byte Value Register (Address Location= 0x079F).
From the TPOH input pin.
00/11 - Configures the Transmit STM-0 POH Processor Block to set Bits-7 through -4 (in the G1 byte of the outbound
VC-3) based upon receive conditions as detected by the corresponding Receive STM-0 POH Processor Block.
01 - Configures the Transmit STM-0 POH Processor Block to set Bits-7 through -4 (in the G1 byte of the outbound
VC-3) based upon the contents within the Transmit G1 Byte Value register (Address Location= 0x079F).
10 - Configures the Transmit STM-0 POH Processor Block to use the TPOH input pin as the source of Bits 1 through
4 (in the G1 byte of the outbound VC-3).
BIT [4:3] - High Order Path Remote Defect Indicator (HP-RDI) Insertion Type[1:0]
These two READ/WRITE bit-fields are used to configure the Transmit STM-0 POH Processor Block to use one of the
three following sources for the HP-RDI bit-fields (e.g., Bits-3 through -1, within the G1 byte of the outbound VC-3).
From the Receive STM-0 POH Processor Block (e g., when it detects various alarm conditions within its
incoming VC-3 data).
From the Transmit G1 Byte Value Register (Address Location = 0x079F).
From the TPOH input pin.
00/11 - Configures the Transmit STM-0 POH Processor Block to set Bits-3 through -1 (in the G1 byte of the outbound
VC-3) based upon receive conditions as detected by the Receive STM-0 POH Processor Block.
01 - Configures the Transmit STM-0 POH Processor Block to set Bits-3 through -1 (in the G1 byte of the outbound
VC-3) based upon the contents within the Transmit G1 Byte Value register.
10 - Configures the Transmit STM-0 POH Processor Block to use the TPOH input pin as the source of Bits 5 through
7 (in the G1 byte of the outbound VC-3).
BIT 2 - C2 Insertion Type
This READ/WRITE bit-field is used to configure the Transmit STM-0 POH Processor Block to use either the Transmit
STM-0 Path - Transmit C2 Byte Value Register or the TPOH input pin as the source for the C2 byte, in the outbound
VC-3.
0 - Configures the Transmit STM-0 POH Processor Block to use the Transmit STM-0 Path - Transmit C2 Value
Register (Address Location= 0x079B).
1 - Configures the Transmit STM-0 POH Processor Block to use the TPOH input as the source for the C2 byte, in the
T
ABLE
169: T
RANSMIT
STM-0 P
ATH
C
ONTROL
R
EGISTER
- B
YTE
0 (TPCR0 0
X
0783)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
F2 Insertion
Type
HP-REI Insertion Type[1:0]
HP-RDI Insertion Type[1:0]
C2 Byte
Insertion
Type
C2 Byte Auto
Insert Mode
Enable
Transmit
AU-AIS
Enable
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0