
PRELIMINARY
XRT86SH221
266
REV. P1.0.5
SDH-TO-PDH FRAMER/MAPPER WITH INTEGRATED 21-CHANNEL E1 SH LIU
BIT 7 - E1 AIS - Event Mask:
This READ/WRITE bit-field permits the user to either enable or disable the "Change of E1 AIS Defect Condition" event
to/from causing the "Change of E1 AIS Defect Condition" interrupt to be generated. If the user enables this feature, then
the VT-Mapper block will assert the "Change of E1 AIS Defect Condition" interrupt in response to either of the following
conditions.
Whenever the VT-Mapper block declares the "E1 AIS" defect condition within the Ingress Direction E1 Data-stream.
Whenever the VT-Mapper block clears the "E1 AIS" defect condition within the Ingress Direction E1 Data Stream.
0 - Configures the VT-Mapper Block to NOT generate the "Change of E1 AIS Defect Condition" interrupt, whenever
it declares or clears the E1 AIS defect condition.
1 - Configures the VT-Mapper Block to generate the "Change of E1 AIS Defect Condition" interrupt, whenever it
declares or clears the "E1 AIS defect condition.
BIT 6 - E1 Loss of Clock Event - Event Mask:
This READ/WRITE bit-field permits the user to either enable or disable the "Change of E1 LOC Defect Condition" event
to/from causing the "Change of E1 LOC Defect Condition" interrupt to be generated. If the user enables this feature,
then the VT-Mapper block will assert the "Change of E1 LOC Defect Condition" interrupt in response to either of the
following conditions.
Whenever the VT-Mapper block declares the "E1 LOC" defect condition within the Ingress Direction E1 Data-stream.
Whenever the VT-Mapper block clears the "E1 LOC" defect condition within the Ingress Direction E1 Data Stream.
0 - Configures the VT-Mapper Block to NOT generate the "Change of E1 LOC Defect Condition" interrupt, whenever
it declares or clears the E1 LOC defect condition.
1 - Configures the VT-Mapper Block to generate the "Change of E1 LOC Defect Condition" interrupt, whenever it
declares or clears the "E1 LOC defect condition.
BIT [5:4] - Reserved:
BIT 3 - Transmit Elastic Store Overflow:
This READ/W1C bit-field indicates whether or not the VT Mapper block has declared a "Transmit Elastic Store Overflow"
event since the last read of this register. The VT-Mapper Block will declare a "Transmit Elastic Store Overflow" event
anytime that the "Transmit FIFO" (within the VT-Mapper block) has experience an "overflow" event.
0 - Indicates that the "Transmit Elastic Store Overflow" event has NOT occurred since the last read of this register.
1 - Indicates that the "Transmit Elastic Store Overflow" event has occurred since the last read of this register.
N
OTE
:
The VT-Mapper block will typically handle "small timing offsets" (between the Ingress Direction E1 signal and
the "Transmit Direction" 19.44MHz or 51.84MHz clock signal via bit-stuffing (as it maps this E1 data into VTs.
However, if this bit-field is set to "1", this is typically a indication of a significant clock frequency accuracy
problem within the system.
BIT [2:0] - Reserved:
T
ABLE
240: C
HANNEL
C
ONTROL
- VT-M
APPER
T
RANSMIT
APS R
EGISTER
1 (VTMTAPSR1 = 0
X
ND56)
B
IT
7
B
IT
6
B
IT
5
B
IT
4
B
IT
3
B
IT
2
B
IT
1
B
IT
0
E1 AIS -
Event Mask
E1 LOC -
Event Mask
Reserved
Transmit
Elastic Store
Overflow
Reserved
R/W
R/W
R/W
R/W
W1C
R/O
R/O
R/O
0
0
0
0
0
0
0
0