
XRT86SH221
PRELIMINARY
51
SDH-TO-PDH FRAMER/MAPPER WITH INTEGRATED 21-CHANNEL E1 SH LIU
REV. P1.0.5
The software can enable or disable the insertion of path AIS-P on detection of any of the aforementioned
conditions. If path AIS insertion is necessary, then an enable signal to the rxstoh_proc block is activated which
causes the rxstoh_proc block to insert all ones in the pertinent bytes.
RXSTOH_CAP BLOCK
The rxstoh_cap block has an 8 bit internal interface bus. The rxstoh_cap block captures the contents of the
SDH overhead for up to 3 STM-0 slots and stores them for access by the external processor. On a read access
from the processor interface, the bit rxstoh_cap block accepts a 9 bit address of the form: xxxxxyyyy where
xxxxx specifies the field number and yyyy specifies the time slot number of the 4 bytes that are requested.
One 944x8 (STM-1) or 256x8 (STM-0) single port RAM is used to capture and hold the SDH OH contents for
the processor of each byte-slice module. The memory is divided into one 512 x 8 (only 432 is used) and one
432 x 8 segments. One segment captures the SDH overhead bytes from the current frame while the other
segment stores the transport overhead bytes from the previous frame. The two segments are swapped after
every frame in the sense that what used to be the current SDH OH byte capture segment is now the holding
segment for the previous frame and vice versa.
When the last SDH overhead byte of the current frame has been written into memory, an interrupt is generated
to notify the software. The contents of the SDH overhead memory will be preserved for one frame (i.e., until the
next SDH OH capture generates an interrupt) for access by the software.
The captured SDH OH bytes are available to the processor via indirect memory registers. The addressing
scheme used to access the SDH OH bytes is shown in
Table 2
. Each access to a captured SDH OH byte
consists of writing the corresponding address into the SDH OH capture indirect address register followed by a
read/write to/from the SDH OH capture indirect data register.
T
ABLE
2: A
DDRESSING
S
CHEME
U
SED
TO
A
CCESS
THE
SDH OH B
YTES
ADDR[9:2]
Byte 3 (MSB)
Byte 2
Byte 1
Byte 0 (LSB)
{5'h00, 2'h0}
A1 (STS-0)
A1 (STM-0)
A1 (STS-2)
A1 (STM-1)
{5'h00, 2'h1}
A1 (STS-4)
A1 (STS-5)
A1 (STS-6)
A1 (STS-7)
{5'h00, 2'h2}
A1 (STS-8)
A1 (STS-9)
A1 (STM-00)
A1 (STM-01)
{5'h00, 2'h3}
unused
unused
unused
Unused
{5'h01, 2'h0}
A2 (STS-0)
A2 (STM-0)
A2 (STS-2)
A2 (STM-1)
{5'h01, 2'h1}
A2 (STS-4)
A2 (STS-5)
A2 (STS-6)
A2 (STS-7)
{5'h01, 2'h2}
A2 (STS-8)
A2 (STS-9)
A2 (STM-00)
A2 (STM-01)
{5'h01, 2'h3}
unused
unused
unused
Unused
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
{5'h1A, 2'h0}
E2
byte 26 (STM-0)
Byte 26 (STS-2)
byte 26 (STM-1)
.
.
.
.
.
{5'h1A, 2'h2}
byte 26 (STS-8)
byte 26 (STS-9)
byte 26 (STM-00)
byte 26 (STM-01)
{5'h1A, 2'hC}
unused
unused
unused
unused
.
.
.
.
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..