
XRT86SH221
PRELIMINARY
255
SDH-TO-PDH FRAMER/MAPPER WITH INTEGRATED 21-CHANNEL E1 SH LIU
REV. P1.0.5
BIT [7:4] - RDI-V Accepted Value[3:0]:
These READ-ONLY bit-fields reflect the most recently value for RDI-V that has been accepted (or validated) by the
Receive VT-Mapper Block. The Receive VT-Mapper block will accept (or validate) a given RDI-V value, once it has
received this same RDI-V value, within RDI-V_Accept_Threshold[3:0] number of consecutive, incoming VT Multi-
frames.
N
OTES
:
1.
These bit-fields are only active if the user has configured the Receive VT-De-Mapper block to support
ERDI-V (Enhanced RDI-V).
2.
These bit-fields reflect the four-bit RDI-V value that the VT De-Mapper block has accepted via the K4
bytes within the incoming VT/TU data-stream.
BIT [3:0] - RDI-V Accept Threshold[3:0]:
These READ/WRITE bit-fields are used to define the RDI-V Validation criteria for the Receive VT-Mapper block. More
specifically, these bit-fields are used to specify the number of consecutive, incoming VT Multi-frame, in which the
Receive VT-Mapper block MUST receive a given RDI-V value BEFORE it validates it and loads it into BIT[7:4] (RDI-V
Accepted Value[3:0]).
BIT 7 - Reserved:
BIT [6:1] - Unused:
BIT 0 - RDI-V Type:
This READ/WRITE bit-field is used to configure the VT-De-Mapper blocks (associated with a given channel) to support
either the SRDI-V (Single Bit - RDI-V) or ERDI-V (Extended - RDI-V) form of signaling. If the user uses only Single-Bit
RDI-V, then the RDI-V indicator will only be transported via Bit 0 (RDI-V) within the V5 byte in a VT-data-stream.
Conversely, if a user uses Extended RDI-V, then the RDI-V indicator will be transported via both Bits 0 (RDI-V) within
the V5 byte, and Bits 3, 2 and 1 within the Z7/K4 byte.
0 - Configures the VT-De-Mapper blocks to use the SRDI-V form of Signaling.
1 - Configures the VT-De-Mapper blocks to use the ERDI-V form of signaling.
N
OTE
:
This configuration setting only applies to the VT-De-Mapper block. If the user wishes to configure the VT-
Mapper block to support either the "SRDI-V" or the "ERDI-V" form of signaling, then he/she must set Bit 1 (RDI-
V Type) within the "Channel Control - VT-Mapper Block - Ingress Direction - Transmit RDI-V Control Register -
Byte 0" to the appropriate state.
T
ABLE
230: C
HANNEL
C
ONTROL
- VT-D
E
M
APPER
E1 D
ROP
C
ONTROL
R
EGISTER
3 (VTDE1DCR3 = 0
X
ND44)
BIT7
BIT6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
RDI-V Accepted Value[3:0]
RDI-V Accept Threshold[3:0]
R/O
R/O
R/O
R/O
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
T
ABLE
231: C
HANNEL
C
ONTROL
- VT-D
E
M
APPER
E1 D
ROP
C
ONTROL
R
EGISTER
2 (VTDE1DCR2 = 0
X
ND45)
BIT7
BIT6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Reserved
Reserved
RDI-V Type
R/O
R/O
R/O
R/O
R/O
R/O
R/O
R/W
0
0
0
0
0
0
0
0