
XRT86SH221
PRELIMINARY
VII
SDH-TO-PDH FRAMER/MAPPER WITH INTEGRATED 21-CHANNEL E1 SH LIU
REV. P1.0.5
= 0
X
ND5B) ................................................................................................................................................................. 267
T
ABLE
244: C
HANNEL
C
ONTROL
- VT-D
E
M
APPER
T
ANDEM
C
ONNECTION
- R
ECEIVE
OEI E
VENT
C
OUNT
R
EGISTER
0 (VTDTCOEIECR =
0
X
ND5F) .................................................................................................................................................................... 268
T
ABLE
245: C
HANNEL
C
ONTROL
- VT-D
E
M
APPER
C
OMPOSITE
S
TATUS
R
EGISTER
1 (VTDCSR1 = 0
X
ND60) ................................ 268
T
ABLE
246: C
HANNEL
C
ONTROL
- VT-D
E
M
APPER
C
OMPOSITE
S
TATUS
R
EGISTER
0 (VTDCSR0 = 0
X
ND61) ................................ 269
T
ABLE
247: C
HANNEL
C
ONTROL
- VT-D
E
M
APPER
T
ANDEM
C
ONNECTION
S
TATUS
R
EGISTER
(VTDTCSR = 0
X
ND62) 271
T
ABLE
248: C
HANNEL
C
ONTROL
- VT-D
E
M
APPER
J2 B
YTE
S
TATUS
R
EGISTER
(VTDJ2BSR = 0
X
ND63) ...................................... 273
T
ABLE
249: C
HANNEL
C
ONTROL
- VT-D
E
M
APPER
C
OMPOSITE
S
TATUS
R
EGISTER
1 (VTDCSR1 = 0
X
ND64) ................................ 274
T
ABLE
250: C
HANNEL
C
ONTROL
- VT-D
E
M
APPER
C
OMPOSITE
S
TATUS
R
EGISTER
0 (VTDCSR0 = 0
X
ND65) ................................ 275
T
ABLE
251: C
HANNEL
C
ONTROL
- VT-D
E
M
APPER
T
ANDEM
C
ONNECTION
I
NTERRUPT
S
TATUS
R
EGISTER
(VTDTCISR = 0
X
ND66) 277
T
ABLE
252: C
HANNEL
C
ONTROL
- VT-D
E
M
APPER
I
NTERRUPT
S
TATUS
R
EGISTER
0 (VTDISR0 = 0
X
ND67) ................................... 279
T
ABLE
253: C
HANNEL
C
ONTROL
- VT-D
E
M
APPER
I
NTERRUPT
E
NABLE
R
EGISTER
2 (VTDIER2 = 0
X
ND68) ................................... 280
T
ABLE
254: C
HANNEL
C
ONTROL
- VT-D
E
-M
APPER
I
NTERRUPT
E
NABLE
R
EGISTER
1 (VTDIER1 = 0
X
ND69) ................................. 281
T
ABLE
255: C
HANNEL
C
ONTROL
- VT-D
E
-M
APPER
T
ANDEM
C
ONNECTION
I
NTERRUPT
E
NABLE
R
EGISTER
(VTDTCIER = 0
X
ND6A) 283
T
ABLE
256: C
HANNEL
C
ONTROL
- VT-D
E
-M
APPER
I
NTERRUPT
E
NABLE
R
EGISTER
0 (VTDIER0 = 0
X
ND6B) ................................. 285
T
ABLE
257: C
HANNEL
C
ONTROL
- VT-D
E
-M
APPER
P
ATH
T
RACE
B
UFFER
C
ONTROL
R
EGISTER
(VTDPTBCR = 0
X
ND71) .............. 286
T
ABLE
258: C
HANNEL
C
ONTROL
- VT-D
E
-M
APPER
A
UTO
AIS C
ONTROL
R
EGISTER
1 (VTDAAISCR1 = 0
X
ND72) ......................... 288
T
ABLE
259: C
HANNEL
C
ONTROL
- VT-D
E
-M
APPER
A
UTO
AIS C
ONTROL
R
EGISTER
0 (VTDAAISCR0 = 0
X
ND73) ......................... 290
T
ABLE
260: C
HANNEL
C
ONTROL
- VT-M
APPER
T
RANSMIT
J2 B
YTE
V
ALUE
R
EGISTER
(VTMJ2VR = 0
X
ND76) ............................... 293
T
ABLE
261: C
HANNEL
C
ONTROL
- VT-M
APPER
T
RANSMIT
N2 B
YTE
V
ALUE
R
EGISTER
(VTMN2VR = 0
X
ND77) ............................. 293
T
ABLE
262: C
HANNEL
C
ONTROL
- VT-M
APPER
T
RANSMIT
P
ATH
T
RACE
M
ESSAGE
C
ONTROL
R
EGISTER
(VTMPTMCR = 0
X
ND79) 294
T
ABLE
263: C
HANNEL
C
ONTROL
- VT-M
APPER
T
RANSMIT
N2 C
ONTROL
R
EGISTER
(VTMN2CR = 0
X
ND7B) ................................. 296
T
ABLE
264: C
HANNEL
C
ONTROL
- VT-M
APPER
T
RANSMIT
T
ANDEM
C
ONNECTION
RDI-V C
ONTROL
R
EGISTER
1 (VTMTCRDICR1 =
0
X
ND7E) .................................................................................................................................................................... 297
T
ABLE
265: C
HANNEL
C
ONTROL
- VT-M
APPER
T
RANSMIT
T
ANDEM
C
ONNECTION
RDI-V C
ONTROL
R
EGISTER
0 (VTMTCRDICR0 =
0
X
ND7F) .................................................................................................................................................................... 298
T
ABLE
266: C
HANNEL
C
ONTROL
- VT-M
APPER
T
RANSMIT
T
ANDEM
C
ONNECTION
ODI-V C
ONTROL
R
EGISTER
1 (VTMTCODICR1 =
0
X
ND82) .................................................................................................................................................................... 300
T
ABLE
267: C
HANNEL
C
ONTROL
- VT-M
APPER
T
RANSMIT
T
ANDEM
C
ONNECTION
ODI-V C
ONTROL
R
EGISTER
0 (VTMTCODICR0 =
0
X
ND83) .................................................................................................................................................................... 301
T
ABLE
268: C
HANNEL
C
ONTROL
- VT-M
APPER
T
RANSMIT
RDI-V C
ONTROL
R
EGISTER
3 (VTMRDICR3 = 0
X
ND84) ..................... 303
T
ABLE
269: C
HANNEL
C
ONTROL
- VT-M
APPER
T
RANSMIT
RDI-V C
ONTROL
R
EGISTER
2 (VTMRDICR2 = 0
X
ND85) ..................... 304
T
ABLE
270: C
HANNEL
C
ONTROL
- VT-M
APPER
T
RANSMIT
RDI-V C
ONTROL
R
EGISTER
1 (VTMRDICR1 = 0
X
ND86) ..................... 305
T
ABLE
271: C
HANNEL
C
ONTROL
- VT-M
APPER
T
RANSMIT
RDI-V C
ONTROL
R
EGISTER
0 (VTMRDICR0 = 0
X
ND87) ..................... 306
T
ABLE
272: R
ECEIVE
J2 T
RACE
I
DENTIFIER
M
ESSAGE
M
EMORY
B
UFFER
(VTDJ2MEM00 = 0
X
NE00 -
VTDJ2MEM3F = 0
X
NE3F) ......................................................................................................................................... 307
T
ABLE
273: R
ECEIVE
N2 A
CCESS
P
OINT
I
DENTIFIER
M
ESSAGE
M
EMORY
B
UFFER
(VTDN2MEM20 = 0
X
NE20
- VTDN2MEM2F = 0
X
NE2F) ...................................................................................................................................... 307
T
ABLE
274: T
RANSMIT
J2 T
RACE
I
DENTIFIER
M
ESSAGE
M
EMORY
B
UFFER
(VTMJ2MEM00 = 0
X
NF00 -
VTMJ2MEM3F = 0
X
NF3F) ........................................................................................................................................ 308
T
ABLE
275: T
RANSMIT
N2 A
CESS
P
OINT
I
DENTIFIER
M
ESSAGE
M
EMORY
B
UFFER
(VTMN2MEM20 = 0
X
NF20
- VTMN2MEM2F = 0
X
NF2F) ..................................................................................................................................... 308
7.0 MICROPROCESSOR INTERFACE TIMING........................................................................................ 309
7.1 MICROPROCESSOR INTERFACE TIMING - INTEL ASYNCHRONOUS MODE.......................................... 309
F
IGURE
55. I
NTEL
-A
SYNCHRONOUS
M
ODE
T
IMING
- W
RITE
O
PERATION
......................................................................................... 309
T
ABLE
276 I
NTEL
A
SYNCHRONOUS
M
ODE
T
IMING
- W
RITE
O
PERATION
......................................................................................... 310
F
IGURE
56. I
NTEL
-A
SYNCHRONOUS
M
ODE
T
IMING
- R
EAD
O
PERATION
.......................................................................................... 310
T
ABLE
277 I
NTEL
A
SYNCHRONOUS
M
ODE
T
IMING
- R
EAD
O
PERATION
........................................................................................... 310
7.2 MICROPROCESSOR INTERFACE TIMING - MOTOROLA ASYNCHRONOUS (68K) MODE...................... 311
F
IGURE
57. M
OTOROLA
-A
SYNCHRONOUS
M
ODE
T
IMING
- W
RITE
O
PERATION
................................................................................ 311
T
ABLE
278 M
OTOROLA
(68K) A
SYNCHRONOUS
M
ODE
T
IMING
I
NFORMATION
- W
RITE
O
PERATION
.................................................. 311
7.2.1 MOTOROLA-ASYNCHRONOUS MODE TIMING - READ OPERATION.................................................................. 312
F
IGURE
58. M
OTOROLA
-A
SYNCHRONOUS
M
ODE
T
IMING
- R
EAD
O
PERATION
................................................................................. 312
T
ABLE
279 M
OTOROLA
(68K) A
SYNCHRONOUS
M
ODE
T
IMING
- R
EAD
O
PERATION
........................................................................ 312
7.3 POWERPC 403 SYNCHRONOUS MODE:...................................................................................................... 313
F
IGURE
59. P
OWER
PC 403 M
ODE
T
IMING
- W
RITE
O
PERATION
.................................................................................................... 313
T
ABLE
280 P
OWER
PC403 M
ODE
T
IMING
- W
RITE
O
PERATION
..................................................................................................... 313
F
IGURE
60. P
OWER
PC 403 M
ODE
T
IMING
- R
EAD
O
PERATION
..................................................................................................... 314
T
ABLE
281 P
OWER
PC403 M
ODE
T
IMING
- R
EAD
O
PERATION
...................................................................................................... 314
7.4 MICROPROCESSOR INTERFACE TIMING - MCP860 SYNCHRONOUS MODE ......................................... 315
F
IGURE
61. MPC86X M
ODE
T
IMING
- W
RITE
O
PERATION
............................................................................................................. 315
T
ABLE
282 MPC86X M
ODE
T
IMING
- W
RITE
O
PERATION
.............................................................................................................. 315
T
ABLE
283 MPC86X T
IMING
I
NFORMATION
- R
EAD
O
PERATION
.................................................................................................... 316
F
IGURE
62. MPC86X M
ODE
T
IMING
- R
EAD
O
PERATION
.............................................................................................................. 316
8.0 INTERFACE TIMING SPECIFICATIONS............................................................................................. 317