
XRT86SH221
PRELIMINARY
125
SDH-TO-PDH FRAMER/MAPPER WITH INTEGRATED 21-CHANNEL E1 SH LIU
REV. P1.0.5
BIT 7 - New S1 Byte Value Interrupt Status
This RESET-upon-READ bit-field indicates whether or not the New S1 Byte Value Interrupt has occurred since the last
read of this register. The Receive STM-0 TOH Processor block will generate the New S1 Byte Value Interrupt, anytime
it has accepted a new S1 byte, from the incoming STM-0 data-stream.
0 - Indicates that the New S1 Byte Value Interrupt has NOT occurred since the last read of this register.
1 - Indicates that the New S1 Byte Value interrupt has occurred since the last read of this register.
N
OTE
:
The user can obtain the value for this most recently accepted value of the S1 byte by reading the Receive STM-
0 Transport S1 Byte Value register (Address Location= 0x0227).
BIT 6 - Change in S1 Byte Unstable Defect Condition Interrupt Status
This RESET-upon-READ bit-field indicates whether or not the Change in S1 Byte Unstable Defect Condition Interrupt
has occurred since the last read of this register. The Receive STM-0 TOH Processor block will generate this interrupt
in response to either of the following events.
Whenever the Receive STM-0 TOH Processor block declares the S1 Byte Unstable defect condition.
Whenever the Receive STM-0 TOH Processor block clears the S1 Byte Unstable defect condition.
0 - Indicates that the Change in S1 Byte Unstable Defect Condition Interrupt has occurred since the last read of this
register.
1 - Indicates that the Change in S1 Byte Unstable Defect Condition Interrupt has not occurred since the last read of
this register.
N
OTE
:
The user can obtain the current S1 Byte Unstable Defect condition by reading the contents of BIT6 (S1 Byte
Unstable Defect Declared) within the Receive STM-0 Transport Status Register - Byte 0 (Address Location=
0x0207).
BIT 5 - Change in Section Trace Message Unstable Defect condition Interrupt Status
This RESET-upon-READ bit-field indicates whether or not the Change in Section Trace Message Unstable defect
condition interrupt has occurred since the last read of this register. The Receive STM-0 TOH Processor block will
generate this interrupt in response to either of the following events.
Whenever the Receive STM-0 TOH Processor block declares the Section Trace Message Unstable defect
condition.
Whenever the Receive STM-0 TOH Processor block clear the Section Trace Message Unstable defect
condition.
Indicates that the Change in Section Trace Message Unstable defect condition interrupt has not occurred since the
last read of this register.
1 - Indicates that the Change in Section Trace Message Unstable defect condition interrupt has occurred since the
last read of this register.
BIT 4 - New Section Trace Message Interrupt Status
This RESET-upon-READ bit-field indicates whether or not the New Section Trace Message interrupt has occurred since
the last read of this register. The Receive STM-0 TOH Processor block will generate this interrupt anytime it has
accepted a new Section Trace Message within the incoming STM-0 data-stream.
T
ABLE
55: R
ECEIVE
STM-0/STM-1 T
RANSPORT
I
NTERRUPT
S
TATUS
R
EGISTER
1 (RTISR1 = 0
X
020A)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
New S1
ByteInter-
rupt Status
Change in
S1 Byte
UnstableDe-
fect Condi-
tionInterrupt
Status
Change in
Section
Trace Mes-
sage Unsta-
ble Defect
Condition
Interrupt Sta-
tus
New Section
Trace Mes-
sage Inter-
rupt Status
Change in
Section
Trace Mes-
sage Mis-
matchDefect
Declared
Interrupt Sta-
tus
Unused
Change in
K1, K2 Byte
Unstable
Defect Cond-
tion Interrupt
Status
NEW K1K2
Byte Value
Interrupt Sta-
tus
RUR
RUR
RUR
RUR
RUR
R/O
RUR
RUR
0
0
0
0
0
0
0
0