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型號：	UPD703270GF-XXX-JBT
元件分類：	微控制器/微處理器
英文描述：	32-BIT, MROM, 20 MHz, RISC MICROCONTROLLER, PQFP100
封裝：	14 X 20 MM, PLASTIC, QFP-100
文件頁數(shù)：	940/1080頁
文件大?。?/td>	6965K
代理商：	UPD703270GF-XXX-JBT

CHAPTER 22 INTERRUPT/EXCEPTION PROCESSING FUNCTION

User’s Manual U16541EJ4V0UD

Table 22-1. Interrupt Source List (4/4)

Classification

A/D conversion completion

DMA0 transfer completion

DMA1 transfer completion

DMA2 transfer completion

DMA3 transfer completion

Key return interrupt

Watch timer interval

Watch timer reference time

AFCAN0 error/IEBus error

AFCAN0 wakeup/

IEBus status

AFCAN0 reception/

IEBus data interrupt

Maskable Interrupt

AFCAN0 transmission/

IEBus error/IEBus status

Notes 1. CAN controller version only

2. IEBus controller version only

Remarks 1. Default Priority: The priority order when two or more maskable interrupt requests occur at the same

time. The highest priority is 0.

The priority order of non-maskable interrupt is INTWDT2 > NMI.

Restored PC:

The value of the program counter (PC) saved to EIPC, FEPC, or DBPC when

interrupt servicing is started. Note, however, that the restored PC when a non-

maskable or maskable interrupt is acknowledged while one of the following

instructions is being executed does not become the nextPC (if an interrupt is

acknowledged during interrupt execution, execution stops, and then resumes after

the interrupt servicing has finished).

Load instructions (SLD.B, SLD.BU, SLD.H, SLD.HU, SLD.W)

Division instructions (DIV, DIVH, DIVU, DIVHU)

PREPARE, DISPOSE instructions (only if an interrupt is generated before the

stack pointer is updated)

The PC value that starts the processing following interrupt/exception processing.

2. The execution address of the illegal instruction when an illegal opcode exception occurs is calculated

by (Restored PC

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