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型號(hào)：	UPD703270GF-XXX-JBT
元件分類：	微控制器/微處理器
英文描述：	32-BIT, MROM, 20 MHz, RISC MICROCONTROLLER, PQFP100
封裝：	14 X 20 MM, PLASTIC, QFP-100
文件頁(yè)數(shù)：	88/1080頁(yè)
文件大小：	6965K
代理商：	UPD703270GF-XXX-JBT

APPENDIX D REVISION HISTORY

User’s Manual U16541EJ4V0UD

Deletion of indication of the preliminary version, addition of Note to the products

under development

Modification of 1.4 Ordering Information

CHAPTER 1 INTRODUCTION

Addition of Note 1 in 2.1 (1) Port pins

Modification of 2.1 (2) Non-port pins

Modification of Table 2-2 Pin Operation States in Various Modes

CHAPTER 2 PIN FUNCTIONS

Modification of Table 3-2 System Register Numbers

Modification of 3.2.2 (4) Program status word (PSW)

Addition of description in 3.2.2 (6) Exception/debug trap status saving registers

(DBPC and DBPSW)

Addition of Caution in Figure 3-1 Image on Address Space

Addition of Note 2 in Figure 3-2 Data Memory Map (Physical Addresses)

Addition of 3.4.4 (4) Programmable peripheral I/O area

Modification of Figure 3-14 Recommended Memory Map

Modification of 3.4.6 Peripheral I/O registers

Modification of 3.4.9 (1) Registers to be set first

Modification of 3.4.9 (2) Accessing specific on-chip peripheral I/O registers

Modification of 3.4.9 (3) Cautions on using flash memory version

Addition of 3.4.9 (4) Restriction on conflict between sld instruction and

interrupt request

CHAPTER 3 CPU FUNCTION

Modification of Table 4-4 Port 0 Alternate-Function Pins

Modification of Table 4-8 Port 5 Alternate-Function Pins

Addition of Remark in 4.3.6 (1) (a), (b)

Modification of Figure 4-8 Block Diagram of Type E-3

Modification of Figure 4-18 Block Diagram of Type N-3

Addition of Note 3 in Table 4-15 Using Port Pin as Alternate-Function Pin

Modification of 4.6.1 (1)

Modification of 4.6.4 Cautions on P05/INTP2/DRST pin

CHAPTER 4 PORT

FUNCTIONS

Modification of 5.1 Features

Addition of Note 2 in Figure 5-1 Data Memory Map: Physical Address

Addition of description in 5.6.2 External wait function

CHAPTER 5 BUS CONTROL

FUNCTION

Modification of Figure 6-1 Clock Generator

Addition of Cautions in 6.3 (2) Internal oscillation mode register (RCM)

Addition of Note in 6.3 (3) CPU operation clock status register (CCLS)

Addition to Table 6-1 Operation Status of Each Clock

Addition of Caution 3 in 6.5.2 (2) Clock control register (CKC)

Addition of description in 6.5.2 (3) Lock register (LOCKR)

Modification of 6.5.3 (1) When PLL is used

CHAPTER 6 CLOCK

GENERATION FUNCTION

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相關(guān)代理商/技術(shù)參數(shù)	參數(shù)描述
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UPD70327L-8-XXX	制造商:未知廠家制造商全稱:未知廠家功能描述:16-Bit Microcontroller
UPD70330GJ-8	制造商:未知廠家制造商全稱:未知廠家功能描述:16-Bit Microcontroller
UPD70330GJ-8-5BG	制造商:未知廠家制造商全稱:未知廠家功能描述:16-Bit Microcontroller

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