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型號：	UPD703270GF-XXX-JBT
元件分類：	微控制器/微處理器
英文描述：	32-BIT, MROM, 20 MHz, RISC MICROCONTROLLER, PQFP100
封裝：	14 X 20 MM, PLASTIC, QFP-100
文件頁數(shù)：	368/1080頁
文件大?。?/td>	6965K
代理商：	UPD703270GF-XXX-JBT

CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ)

User’s Manual U16541EJ4V0UD

16-bit timer/event counter Q waits for a trigger when the TQ0CE bit is set to 1. When the trigger is generated, the

16-bit counter is cleared from FFFFH to 0000H, starts counting at the same time, and outputs a PWM waveform from

the TOQ0k pin. If the trigger is generated again while the counter is operating, the counter is cleared to 0000H and

restarted. (The output of the TOQ00 pin is inverted. The TOQ0k pin outputs a high-level regardless of the status

(high/low) when a trigger is generated.)

The active level width, cycle, and duty factor of the PWM waveform can be calculated as follows.

Active level width = (Set value of TQ0CCRk register)

× Count clock cycle

Cycle = (Set value of TQ0CCR0 register + 1)

× Count clock cycle

Duty factor = (Set value of TQ0CCRk register)/(Set value of TQ0CCR0 register + 1)

The compare match request signal INTTQ0CC0 is generated when the 16-bit counter counts next time after its

count value matches the value of the CCR0 buffer register, and the 16-bit counter is cleared to 0000H. The compare

match interrupt request signal INTTQ0CCk is generated when the count value of the 16-bit counter matches the value

of the CCRk buffer register.

The value set to the TQ0CCRm register is transferred to the CCRm buffer register when the count value of the 16-

bit counter matches the value of the CCR0 buffer register and the 16-bit counter is cleared to 0000H.

The valid edge of an external trigger input signal, or setting the software trigger (TQ0CTL1.TQ0EST bit) to 1 is

used as the trigger.

Figure 8-18. Setting of Registers in External Trigger Pulse Output Mode (1/3)

(a) TMQ0 control register 0 (TQ0CTL0)

Select count clock

0: Stop counting

1: Enable counting

TQ0CKS2 TQ0CKS1 TQ0CKS0

Note The setting is invalid when the TQ0CTL1.TQ0EEE bit = 1.

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