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型號(hào)：	UPD703270GF-XXX-JBT
元件分類：	微控制器/微處理器
英文描述：	32-BIT, MROM, 20 MHz, RISC MICROCONTROLLER, PQFP100
封裝：	14 X 20 MM, PLASTIC, QFP-100
文件頁(yè)數(shù)：	602/1080頁(yè)
文件大小：	6965K
代理商：	UPD703270GF-XXX-JBT

CHAPTER 17 I

User’s Manual U16541EJ4V0UD

Matching address detection

Addresses do not match.

Addresses match.

Condition for clearing (COIn bit = 0)

Condition for setting (COIn bit = 1)

When a start condition is detected

When a stop condition is detected

Cleared by LRELn bit = 1 (communication save)

When the IICEn bit changes from 1 to 0 (operation

When the received address matches the local

address (SVAn register) (set at the rising edge of the

eighth clock).

Transmit/receive status detection

Receive status (other than transmit status). The SDA0n line is set to high impedance.

Transmit status. The value in the SO latch is enabled for output to the SDA0n line (valid starting at

the falling edge of the first byte’s ninth clock).

Condition for clearing (TRCn bit = 0)

Condition for setting (TRCn bit = 1)

When a stop condition is detected

Cleared by LRELn bit = 1 (communication save)

When the IICEn bit changes from 1 to 0 (operation

Cleared by IICCn.WRELn bit = 1Note

When the ALDn bit changes from 0 to 1 (arbitration

When “1” is output to the first byte’s LSB (transfer

direction specification bit)

When a start condition is detected

When not used for communication

When a start condition is generated

When “0” is output to the first byte’s LSB (transfer

direction specification bit)

When “1” is input by the first byte’s LSB (transfer

direction specification bit)

ACK detection

ACK was not detected.

ACK was detected.

Condition for clearing (ACKDn bit = 0)

Condition for setting (ACKD bit = 1)

When a stop condition is detected

At the rising edge of the next byte’s first clock

Cleared by LRELn bit = 1 (communication save)

When the IICEn bit changes from 1 to 0 (operation

After the SDA0n bit is set to low level at the rising

edge of the SCL0n pin’s ninth clock

Note The TRCn bit is cleared to 0 and SDA0n line becomes high impedance when the WRELn bit is

set to 1 and the wait state is canceled to 0 at the ninth clock by TRCn bit = 1.

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