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型號(hào)：	UPD703270GF-XXX-JBT
元件分類：	微控制器/微處理器
英文描述：	32-BIT, MROM, 20 MHz, RISC MICROCONTROLLER, PQFP100
封裝：	14 X 20 MM, PLASTIC, QFP-100
文件頁(yè)數(shù)：	607/1080頁(yè)
文件大?。?/td>	6965K
代理商：	UPD703270GF-XXX-JBT

CHAPTER 17 I

User’s Manual U16541EJ4V0UD

(4) IIC clock select registers 0 to 2 (IICCL0 to IICCL2)

The IICCL0 to IICCL2 registers set the transfer clock for the I

These registers can be read or written in 8-bit or 1-bit units. However, the CLDn and DADn bits are read-only.

Set the IICCLn register when the IICCn.IICEn bit = 0.

The SMCn, CLn1, and CLn0 bits are set by the combination of the IICXn.CLXn bit and the OCKSTHm,

OCKSm1, and OCKSm0 bits of the OCKSm register (see 17.4 (6) I

2C0n transfer clock setting method) (n = 0

to 2, m = 0, 1).

Reset input clears these registers to 00H.

After reset: 00H

Address: IICCL0 FFFFFD84H, IICCL1 FFFFFD94H, IICCL2 FFFFFDA4H

(n = 0 to 2)

Detection of SCL0n pin level (valid only when IICCn.IICEn bit = 1)

The SCL0n pin was detected at low level.

The SCL0n pin was detected at high level.

Condition for clearing (CLDn bit = 0)

Condition for setting (CLDn bit = 1)

When the SCL0n pin is at low level

When the IICEn bit = 0 (operation stop)

When the SCL0n pin is at high level

Detection of SDA0n pin level (valid only when IICEn bit = 1)

The SDA0n pin was detected at low level.

The SDA0n pin was detected at high level.

Condition for clearing (DADn bit = 0)

Condition for setting (DAD0n bit = 1)

When the SDA0n pin is at low level

When the IICEn bit = 0 (operation stop)

When the SDA0n pin is at high level

Operation mode switching

Operation in standard mode.

Operation in high-speed mode.

Digital filter operation control

Digital filter off.

Digital filter on.

The digital filter can be used only in high-speed mode.

In high-speed mode, the transfer clock does not vary regardless of the DFCn bit setting (on/off).

The digital filter is used to eliminate noise in high-speed mode.

Note Bits 4 and 5 of IICCLn are read-only bits.

Be sure to clear bits 7 and 6 of IICCLn to 0.

When the IICCn.IICEn bit = 0, 0 is read when reading the CLDn and DADn bits.

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