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型號：	UPD703270GF-XXX-JBT
元件分類：	微控制器/微處理器
英文描述：	32-BIT, MROM, 20 MHz, RISC MICROCONTROLLER, PQFP100
封裝：	14 X 20 MM, PLASTIC, QFP-100
文件頁數(shù)：	561/1080頁
文件大?。?/td>	6965K
代理商：	UPD703270GF-XXX-JBT

CHAPTER 16 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB)

User’s Manual U16541EJ4V0UD

Communication start trigger invalid

Communication start trigger valid

Specification of start transfer disable/enable

In master mode

This bit enables or disables the communication start trigger.

(a) In single transmission or transmission/reception mode, or continuous

transmission or continuous transmission/reception mode

The setting of the CBnSCE bit has no influence on communication operation.

(b) In single reception mode

Clear the CBnSCE bit to 0 before reading the last receive data because

reception is started by reading the receive data (CBnRX register) to disable

the reception startup

Clear the CBnSCE bit to 0 one communication clock before reception of the

last data is completed to disable the reception startup after the last data is

In slave mode

This bit enables or disables the communication start trigger.

Set the CBnSCE bit to 1.

[Usage of CBnSCE bit]

In single reception mode

<1>When reception of the last data is completed by INTCBnR interrupt

servicing, clear the CBnSCE bit to 0 before reading the CBnRX register.

<2>After confirming the CBnSTR.CBnTSF bit = 0, clear the CBnRXE bit to 0 to

disable reception.

To continue reception, set the CBnSCE bit to 1 to start up the next reception

by dummy-reading the CBnRX register.

In continuous reception mode

<1>Clear the CBnSCE bit to 0 during the reception of the last data by INTCBnR

interrupt servicing.

<2>Read the CBnRX register.

<3>Read the last reception data by reading the CBnRX register after

acknowledging the CBnTIR interrupt.

<4>After confirming the CBnSTR.CBnTSF bit = 0, clear the CBnRXE bit to 0 to

disable reception.

To continue reception, set the CBnSCE bit to 1 to wait for the next reception

by dummy-reading the CBnRX register.

Notes 1. If the CBnSCE bit is read while it is 1, the next communication operation is started.

2. The CBnSCE bit is not cleared to 0 one communication clock before the completion

of the last data reception, the next communication operation is automatically

Be sure to clear bits 3 and 2 to 0.

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