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型號(hào)：	UPD703270GF-XXX-JBT
元件分類：	微控制器/微處理器
英文描述：	32-BIT, MROM, 20 MHz, RISC MICROCONTROLLER, PQFP100
封裝：	14 X 20 MM, PLASTIC, QFP-100
文件頁(yè)數(shù)：	1007/1080頁(yè)
文件大小：	6965K
代理商：	UPD703270GF-XXX-JBT

CHAPTER 25 RESET FUNCTIONS

User’s Manual U16541EJ4V0UD

25.3.2 Reset operation by watchdog timer 2

When watchdog timer 2 is set to the reset operation mode due to overflow, upon watchdog timer 2 overflow

(WDT2RES signal generation), a system reset is executed and the hardware is initialized to the initial status.

Following watchdog timer 2 overflow, the reset status is entered and lasts the predetermined time (analog delay),

and the reset status is then automatically released.

The main clock oscillator is stopped during the reset period.

Table 25-2. Hardware Status During Watchdog Timer 2 Reset Operation

During Reset

Main clock oscillator (fX)

Oscillation stops

Oscillation starts

Subclock oscillator (fXT)

Oscillation continues

Internal oscillator

Oscillation stops

Oscillation starts

Peripheral clock (fXX to fXX/1,024)

Operation stops

Operation starts after securing oscillation

stabilization time

Internal system clock (fXX),

CPU clock (fCPU)

Operation stops

Operation starts after securing oscillation

stabilization time (initialized to fXX/8)

Program execution after securing

oscillation stabilization time

Watchdog timer 2

Operation stops (initialized to 0)

Counts up from 0 with internal oscillation

clock as source clock.

Internal RAM

Undefined if power-on reset or CPU access and reset input conflict (data is damaged).

Otherwise value immediately after reset input is retained

I/O lines (ports/alternate-function

High impedance

On-chip peripheral I/O register

Initialized to specified status, OCDM register retains its value.

On-chip peripheral functions other

Operation stops

Operation can be started after securing

oscillation stabilization time.

The firmware of the V850ES/SG2 uses part of the internal RAM after the internal system reset operation

has been released because it supports a boot swap function. Therefore, the contents of some RAM areas

are not retained on power-on reset. For details, see 25.3.4 Operation after reset release.

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