
User’s Manual U16541EJ4V0UD
1070
APPENDIX D REVISION HISTORY
D.1
Major Revisions in This Edition
(1/4)
Page
Description
Throughout
Deletion of indication “under development” for the following products (developed)
GF package
PD703260, 703260Y, 703261, 703261Y, 703270, 703270Y, 703271Y
GC package
PD703260, 703260Y, 703262, 703262Y, 703263, 703263Y, 703270, 703270Y, 703272, 703272Y,
703273, 703273Y, 703280, 703280Y, 703281, 703281Y, 703282, 703282Y, 703283, 703283Y
p. 25
Modification of Table 1-2 V850ES/SJ2 Product List
p. 49
Modification of 2.2 Pin States
p. 54
Addition of 2.4 Cautions
pp. 98, 99
Modification of 3.4.9 (2) Accessing specific on-chip peripheral I/O registers and (3) System reserved
area
p. 110
Addition of Caution to Table 4-5 Port 1 Alternate-Function Pins
p. 110
Modification of Caution 1 and addition of Caution 2 in 4.3.2 (2) Port 1 mode register (PM1)
p. 111
Modification of Table 4-6 Port 3 Alternate-Function Pins
p. 118
Modification of Table 4-7 Port 4 Alternate-Function Pins
p. 121
Addition of Caution 1 to Table 4-8 Port 5 Alternate-Function Pins
p. 148
Modification of Figure 4-7 Block Diagram of Type D-3
p. 149
Modification of Figure 4-8 Block Diagram of Type E-3
p. 154
Modification of Figure 4-13 Block Diagram of Type G-5
p. 155
Modification of Figure 4-14 Block Diagram of Type G-6
p. 156
Addition of Figure 4-15 Block Diagram of Type G-12
p. 159
Modification of Figure 4-18 Block Diagram of Type N-2
p. 160
Modification of Figure 4-19 Block Diagram of Type N-3
p. 167
Modification of Figure 4-26 Block Diagram of Type U-10
p. 168
Modification of Figure 4-27 Block Diagram of Type U-11
p. 175
Modification of Caution in Table 4-15 Using Port Pin as Alternate-Function Pin
p. 186
Addition of 4.6.5 Cautions on P10, P11, and P53 pins when power is turned on
p. 187
Modification of 5.1 Features
p. 217
Addition and modification of description in 6.3 (1) Processor clock control register (PCC)
p. 218
Addition of description in 6.3 (1) (a) Example of setting main clock operation
→ subclock operation
p. 219
Addition of Caution in 6.3 (1) (b) Example of setting subclock operation
→ main clock operation
p. 225
Addition of Caution 2 to 6.5.2 (4) PLL lockup time specification register (PLLS)
p. 237
Modification of 7.4 (7) TMPn capture/compare register 0 (TPnCCR0)
p. 239
Modification of 7.4 (8) TMPn capture/compare register 1 (TPnCCR1)
p. 241
Modification of 7.4 (9) TMPn counter read buffer register (TPnCNT)
p. 244
Modification of Figure 7-4 Register Setting for Interval Timer Mode Operation
p. 253
Modification of Figure 7-10 Basic Timing in External Event Count Mode
p. 254
Modification of Figure 7-11 Register Setting for Operation in External Event Count Mode
p. 257
Addition of Caution 2 to 7.5.2 (2) Operation timing in external event count mode