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型號(hào)：	UPD703270GF-XXX-JBT
元件分類：	微控制器/微處理器
英文描述：	32-BIT, MROM, 20 MHz, RISC MICROCONTROLLER, PQFP100
封裝：	14 X 20 MM, PLASTIC, QFP-100
文件頁(yè)數(shù)：	523/1080頁(yè)
文件大?。?/td>	6965K
代理商：	UPD703270GF-XXX-JBT

CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA)

User’s Manual U16541EJ4V0UD

When the UAnPWR bit = 0 or the UAnTXE bit = 0 has been set.

When, following transfer completion, there was no next data transfer

from UAnTX register

Write to UAnTX register

Transfer status flag

(n = 0 to 2)

After reset: 00H

Address: UA0STR FFFFFA04H, UA1STR FFFFFA14H,

UA2STR FFFFFA24H

The UAnTSF bit is always 1 when performing continuous transmission. When

initializing the transmission unit, check that the UAnTSF bit = 0 before performing

initialization. The transmit data is not guaranteed when initialization is performed

while the UAnTSF bit = 1.

When the UAnPWR bit = 0 or the UAnRXE bit = 0 has been set.

When 0 has been written

When parity of data and parity bit do not match during reception.

Parity error flag

The operation of the UAnPE bit is controlled by the settings of the

UAnCTL0.UAnPS1 and UAnCTL0.UAnPS0 bits.

The UAnPE bit can be read and written, but it can only be cleared by writing 0 to it, and

it cannot be set by writing 1 to it. When 1 is written to this bit, the value is retained.

When the UAnPWR bit = 0 or the UAnRXE bit = 0 has been set

When 0 has been written

When no stop bit is detected during reception

Framing error flag

Only the first bit of the receive data stop bits is checked, regardless of the value

of the UAnCTL0.UAnSL bit.

The UAnFE bit can be both read and written, but it can only be cleared by

writing 0 to it, and it cannot be set by writing 1 to it. When 1 is written to this bit,

the value is retained.

When the UAnPWR bit = 0 or the UAnRXE bit = 0 has been set.

When 0 has been written

When receive data has been set to the UAnRX register and the next

receive operation is completed before that receive data has been read

Overrun error flag

When an overrun error occurs, the data is discarded without the next receive data

being written to the receive buffer.

The UAnOVE bit can be both read and written, but it can only be cleared by writing

0 to it. When 1 is written to this bit, the value is retained.

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