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型號：	UPD703270GF-XXX-JBT
元件分類：	微控制器/微處理器
英文描述：	32-BIT, MROM, 20 MHz, RISC MICROCONTROLLER, PQFP100
封裝：	14 X 20 MM, PLASTIC, QFP-100
文件頁數(shù)：	799/1080頁
文件大小：	6965K
代理商：	UPD703270GF-XXX-JBT

CHAPTER 19 CAN CONTROLLER

User’s Manual U16541EJ4V0UD

19.6 Registers

Accessing the CAN controller registers is prohibited in the following statuses. For details, refer

to 3.4.9 (2) Accessing specific on-chip peripheral I/O registers.

When the CPU operates with the subclock and the main clock oscillation is stopped

When the CPU operates with the internal oscillation clock

m = 00 to 31

(1) CAN0 global control register (C0GMCTRL)

The C0GMCTRL register is used to control the operation of the CAN module.

After reset: 0000H

Bit enabling access to message buffer register, transmit/receive history registers

Write access and read access to the message buffer register and the transmit/receive history list registers is

Write access and read access to the message buffer register and the transmit/receive history list registers is

Cautions 1. While the MBON bit is cleared (to 0), software access to the message buffers

(C0MDATA0m,

C0MDATA1m,

C0MDATA01m,

C0MDATA2m,

C0MDATA3m,

C0MDATA23m,

C0MDATA4m,

C0MDATA5m,

C0MDATA45m,

C0MDATA6m,

C0MDATA7m, C0MDATA67m, C0MDLCm, C0MCONFm, C0MIDLm, C0MIDHm, and

C0MCTRLm), or registers related to transmit history or receive history (C0LOPT,

C0TGPT, C0LIPT, and C0RGPT) is disabled.

2. This bit is read-only. Even if 1 is written to the MBON bit while it is 0, the value of the

MBON bit does not change, and access to the message buffer registers, or registers

related to transmit history or receive history remains disabled.

When the CAN sleep mode/CAN stop mode is entered, or when the GOM bit is cleared to 0, the

MBON bit is cleared to 0. When the CAN sleep mode/CAN stop mode is released, or when the

GOM bit is set to 1, the MBON bit is set to 1.

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