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型號：	UPD703270GF-XXX-JBT
元件分類：	微控制器/微處理器
英文描述：	32-BIT, MROM, 20 MHz, RISC MICROCONTROLLER, PQFP100
封裝：	14 X 20 MM, PLASTIC, QFP-100
文件頁數(shù)：	78/1080頁
文件大?。?/td>	6965K
代理商：	UPD703270GF-XXX-JBT

APPENDIX C INSTRUCTION SET LIST

User’s Manual U16541EJ4V0UD

r r r r r 0 0 1 1 0 1 R RRR R

←GR[reg2]–GR[reg1]

r r r r r 0 0 1 1 0 0 R RRR R

←GR[reg1]–GR[reg2]

00000000010RRRRR

←(PC+2) + (GR [reg1] logically shift left by 1)

←(PC+2) + (sign-extend

(Load-memory (adr,Halfword))

logically shift left by 1

00000000101RRRRR

←sign-extend

(GR[reg1] (7 : 0))

00000000111RRRRR

←sign-extend

(GR[reg1] (15 : 0))

000 00 11 11 11 i iiii

0000000100000000

←PC+4 (Restored PC)

←Interrupt code

(when vector is 00H to 0FH)

(when vector is 10H to 1FH)

r r r r r 0 0 1 0 1 1 R RRR R

←GR[reg2] AND GR[reg1]

bit#3,disp16[reg1]

11bbb111110RRRRR

dddddddddddddddd

←GR[reg1]+sign-extend(disp16)

←Not (Load-memory-bit (adr,bit#3))

reg2, [reg1]

r r r r r 1 1 1 1 1 1 R RRR R

0000000011100110

←Not (Load-memory-bit (adr,reg2))

r r r r r 0 0 1 0 0 1 R RRR R

←GR[reg2] XOR GR[reg1]

imm16,reg1,reg2

r r r r r 1 1 0 1 0 1 R RRR R

iiiiiiiiiiiii iii

←GR[reg1] XOR zero-extend (imm16)

00000000100RRRRR

←zero-extend (GR[reg1] (7 : 0))

00000000110RRRRR

←zero-extend (GR[reg1] (15 : 0))

Notes 1.

dddddddd: Higher 8 bits of disp9.

3 if there is an instruction that rewrites the contents of the PSW immediately before.

If there is no wait state (3 + the number of read access wait states).

n is the total number of list12 load registers. (According to the number of wait states. Also, if there

are no wait states, n is the total number of list12 registers. If n = 0, same operation as when n = 1)

RRRRR: other than 00000.

The lower halfword data only are valid.

ddddddddddddddddddddd: The higher 21 bits of disp22.

ddddddddddddddd: The higher 15 bits of disp16.

According to the number of wait states (1 if there are no wait states).

10. b: bit 0 of disp16.

11. According to the number of wait states (2 if there are no wait states).

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