
APPENDIX C INSTRUCTION SET LIST
User’s Manual U16541EJ4V0UD
1063
C.2 Instruction Set (in Alphabetical Order)
(1/6)
Execution
Clock
Flags
Mnemonic
Operand
Opcode
Operation
i
r
l
CY OV
S
Z SAT
reg1,reg2
r r r r r 0 0 1 1 1 0 R RRR R
GR[reg2]
←GR[reg2]+GR[reg1]
1
×
ADD
imm5,reg2
r r r r r 0 1 0 010i i iii
GR[reg2]
←GR[reg2]+sign-extend(imm5)
1
×
ADDI
imm16,reg1,reg2
r r r r r 1 1 0 0 0 0 R RRR R
iiiiii iiii iii iii
GR[reg2]
←GR[reg1]+sign-extend(imm16)
1
×
AND
reg1,reg2
r r r r r 0 0 1 0 1 0 R RRR R
GR[reg2]
←GR[reg2]AND GR[reg1]
1
0
×
ANDI
imm16,reg1,reg2
r r r r r 1 1 0 1 1 0 R RRR R
iiiiii iiii iii iii
GR[reg2]
←GR[reg1]AND zero-extend(imm16)
1
0
×
When conditions
are satisfied
2
Note2
2
Note2
2
Note2
Bcond
disp9
ddddd1011dddcccc
Note 1
if conditions are satisfied
then PC
←PC+sign-extend(disp9)
When conditions
are not satisfied
1
BSH
reg2,reg3
r r r r r 1 1 1 1 1 1 0 0 0 0 0
wwwww01101000010
GR[reg3]
←GR[reg2] (23 : 16) ll GR[reg2] (31 : 24) ll
GR[reg2] (7 : 0) ll GR[reg2] (15 : 8)
1
×
0
×
BSW
reg2,reg3
r r r r r 1 1 1 1 1 1 0 0 0 0 0
wwwww01101000000
GR[reg3]
←GR[reg2] (7 : 0) ll GR[reg2] (15 : 8) ll GR
[reg2] (23 : 16) ll GR[reg2] (31 : 24)
1
×
0
×
CALLT
imm6
0000001 000ii iiii
CTPC
←PC+2(return PC)
CTPSW
←PSW
adr
←CTBP+zero-extend(imm6 logically shift left by 1)
PC
←CTBP+zero-extend(Load-memory(adr,Halfword))
4
bit#3,disp16[reg1]
10bbb111110RRRRR
dddddddddddddddd
adr
←GR[reg1]+sign-extend(disp16)
Z flag
←Not(Load-memory-bit(adr,bit#3))
Store-memory-bit(adr,bit#3,0)
3
Note3
3
Note3
3
Note3
×
CLR1
reg2,[reg1]
r r r r r 1 1 1 1 1 1 R RRR R
0000000011100100
adr
←GR[reg1]
Z flag
←Not(Load-memory-bit(adr,reg2))
Store-memory-bit(adr,reg2,0)
3
Note3
3
Note3
3
Note3
×
cccc,imm5,reg2,reg3
r r r r r 1 1 1 111i i iii
wwwww011000cccc0
if conditions are satisfied
then GR[reg3]
←sign-extended(imm5)
else GR[reg3]
←GR[reg2]
1
CMOV
cccc,reg1,reg2,reg3
r r r r r 1 1 1 1 1 1 R RRR
wwwww011001cccc0
if conditions are satisfied
then GR[reg3]
←GR[reg1]
else GR[reg3]
←GR[reg2]
1
reg1,reg2
r r r r r 0 0 1 1 1 1 R RRR R
result
←GR[reg2]–GR[reg1]
1
×
CMP
imm5,reg2
r r r r r 0 1 0 011i i iii
result
←GR[reg2]–sign-extend(imm5)
1
×
CTRET
0000011111100000
0000000101000100
PC
←CTPC
PSW
←CTPSW
3
R
DBRET
0000011111100000
0000000101000110
PC
←DBPC
PSW
←DBPSW
3
R