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型號(hào)：	UPD703270GF-XXX-JBT
元件分類：	微控制器/微處理器
英文描述：	32-BIT, MROM, 20 MHz, RISC MICROCONTROLLER, PQFP100
封裝：	14 X 20 MM, PLASTIC, QFP-100
文件頁數(shù)：	484/1080頁
文件大小：	6965K
代理商：	UPD703270GF-XXX-JBT

CHAPTER 13 A/D CONVERTER

User’s Manual U16541EJ4V0UD

13.5 Operation

13.5.1 Basic operation

<1> Set the operation mode, trigger mode, and conversion time for executing A/D conversion by using the

ADA0M0, ADA0M1, ADA0M2, and ADA0S registers. When the ADA0CE bit of the ADA0M0 register is set,

conversion is started in the software trigger mode and the A/D converter waits for a trigger in the external or

timer trigger mode.

<2> When A/D conversion is started, the voltage input to the selected analog input channel is sampled by the

sample & hold circuit.

<3> When the sample & hold circuit samples the input channel for a specific time, it enters the hold status, and

holds the input analog voltage until A/D conversion is complete.

<4> Set bit 9 of the successive approximation register (SAR). The tap selector selects (1/2) AVREF0 as the voltage

tap of the series resistor string.

<5> The voltage difference between the voltage of the series resistor string and the analog input voltage is

compared by the voltage comparator. If the analog input voltage is higher than (1/2) AVREF0, the MSB of the

SAR register remains set. If it is lower than (1/2) AVREF0, the MSB is reset.

<6> Next, bit 8 of the SAR register is automatically set and the next comparison is started. Depending on the

value of bit 9, to which a result has been already set, the voltage tap of the series resistor string is selected

Bit 9 = 1: (3/4) AVREF0

Bit 9 = 0: (1/4) AVREF0

This voltage tap and the analog input voltage are compared and, depending on the result, bit 8 is

manipulated as follows.

Analog input voltage

≥ Voltage tap: Bit 8 = 1

Analog input voltage

≤ Voltage tap: Bit 8 = 0

<7> This comparison is continued to bit 0 of the SAR register.

<8> When comparison of the 10 bits is complete, the valid digital result is stored in the SAR register, which is then

transferred to and stored in the ADA0CRn register. After that, an A/D conversion end interrupt request signal

(INTAD) is generated.

<9> In one-shot select mode, conversion is stopped

Note. In one-shot scan mode, conversion is stopped after

scanning once

Note. In continuous select mode, repeat steps <2> to <8> until the ADA0M0.ADA0CE bit is

cleared to 0. In continuous scan mode, repeat steps <2> to <8> for each channel.

Note In the external trigger mode, timer trigger mode 0, or timer trigger mode 1, the trigger standby status

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