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參數(shù)資料
| 型號： | T7698 |
| 廠商： | Lineage Power |
| 英文描述： | Quad T1/E1 Line Interface and Octal T1/E1 Monitor(四T1/E1線接口和八T1/E1監(jiān)控器) |
| 中文描述： | 四T1/E1線路接口和八路的T1/E1監(jiān)視器（四個T1/E1線接口和八T1/E1的監(jiān)控器） |
| 文件頁數(shù)： | 99/112頁 |
| 文件大小： | 1359K |
| 代理商： | T7698 |
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Data Sheet
January 1999
T7698 Quad T1/E1 Line Interface and Octal T1/E1 Monitor
99
Lucent Technologies Inc.
XCLK Reference Clock
(continued)
Primary Line Rate XCLK Reference Clock and Internal Reference Clock Synthesizer
In some applications, it is more desirable to provide a reference clock at the primary data rate. In such cases, the
LIU can utilize an internal 16x clock synthesizer allowing the XCLK pin to accept a primary data rate clock. The
specifications for XCLK using a primary rate reference clock are defined in Table 110.
Table 110. XCLK (1x, CLKS = 1) Timing Specifications
* When JABW0 = 1 and the jitter attenuator is used in the receive data path, the tolerance on XCLK should be tightened to ±20 ppm in order to
meet the jitter accommodation requirements of TBR12/13 as given in G.823 for line data rates of ±50 ppm.
If XCLK is used as the source for AIS (see Alarm Indication Signal Generator (XAIS) on page 31), it must meet the nominal transmission
specifications of 1.544 MHz ± 32 ppm for DS1 (T1), or 2.048 MHz ± 50 ppm for CEPT (E1).
The data rate reference clock and the internal clock synthesizer is selected when CLKS = 1. In this mode, a valid
and stable data rate reference clock must be applied to the XCLK pin before and during the time a hardware reset
is activated (RESET = 0). The reset must be held active for a minimum of two data rate clock periods to ensure
proper resetting of the clock synthesizer circuit. Upon the deactivation of the reset pin (RESET = 1), the LIU will
extend the reset condition internally for approximately 1/2(2
12
– 1) line clock periods, or 1.3 ms for DS1 and
1 ms for CEPT after the hardware reset pin has become inactive, allowing the clock synthesizer additional time to
settle. No activity such as microprocessor read/write should be performed during this period. The device will be
operational 2.7 ms after the deactivation of the hardware reset pin. Issuing an LIU software restart (LIU_REG2
bit 5 (RESTART) = 1) does not impact the clock synthesizer circuit.
Power Supply Bypassing
External bypassing is required for all channels. A 1.0 μF capacitor must be connected between V
DD
X and GNDX.
In addition, a 0.1 μF capacitor must be connected between V
DDD
and GND
D
, and a 0.1 μF capacitor must be con-
nected between V
DDA
and GND
A
. Ground plane connections are required for GNDX, GND
D
, and GND
A
. Power
plane connections are also required for V
DD
X and V
DDD
. The need to reduce high-frequency coupling into the ana-
log supply (V
DDA
) may require an inductive bead to be inserted between the power plane and the V
DDA
pin of every
channel.
Capacitors used for power supply bypassing should be placed as close as possible to the device pins for maximum
effectiveness.
Parameter
Value
Unit
Min
Typ
Max
Frequency:
DS1
CEPT
Range*,
Duty Cycle
Rise and Fall Times
(10%—90%)
—
—
1.544
2.048
—
—
—
—
—
100
60
5
MHz
MHz
ppm
%
ns
–100
40
—
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