參數(shù)資料
型號： T7698
廠商： Lineage Power
英文描述： Quad T1/E1 Line Interface and Octal T1/E1 Monitor(四T1/E1線接口和八T1/E1監(jiān)控器)
中文描述： 四T1/E1線路接口和八路的T1/E1監(jiān)視器（四個T1/E1線接口和八T1/E1的監(jiān)控器）
文件頁數(shù)： 16/112頁
文件大?。?/td> 1359K
代理商： T7698
Data Sheet
January 1999
T7698 Quad T1/E1 Line Interface and Octal T1/E1 Monitor
16
Lucent Technologies Inc.
Microprocessor Interface
Overview
The device is equipped with a microprocessor interface that can operate with most commercially available micro-
processors. Inputs MPMUX and MPMODE (pins 20 and 21) are used to configure this interface into one of four
possible modes, as shown in Table 3. The MPMUX setting selects either a multiplexed 8-bit address/data bus
(AD[7:0]) or a demultiplexed 4-bit address bus (A[3:0]) and an 8-bit data bus (AD[7:0]). The MPMODE setting
selects the associated set of control signals required to access a set of registers within the device.
When the microprocessor interface is configured to operate in the multiplexed address/data bus modes (MPMUX =
1), the user has access to an internal chip select function that allows the microprocessor to selectively read/write a
specific T7698 in a multiple T7698 environment (see the Internal Chip Select Function section).
The microprocessor interface can operate at speeds up to 16.384 MHz in interrupt-driven or polled
mode without requiring any wait-states. For microprocessors operating at greater than 16.384 MHz, the
RDY_DTACK output is used to introduce wait-states in the read/write cycles.
In the interrupt-driven mode, one or more device alarms will assert the active-high INT output (pin 25) once per
alarm activation. After the microprocessor reads the alarm status registers, the INT output will deassert. In the
polled mode, however, the microprocessor monitors the various device alarm status by periodically reading the
alarm status registers without the use of INT (pin 25). A variety of LIU mask controls are available for control of the
INT pin.
Microprocessor Configuration Modes
Table 3 highlights the four microprocessor modes controlled by the MPMUX and MPMODE inputs (pins 20 and 21).
Table 3. Microprocessor Configuration Modes
Mode
MPMODE
MPMUX
Address/Data Bus
Generic Control, Data, and
Output Pin Names
CS
,
AS
,
DS
, R/
W
, A[3:0], AD[7:0], INT,
DTACK
CS
,
AS
,
DS
, R
/W
, AD[7:0], INT,
DTACK
CS
, ALE,
RD
,
WR
, A[3:0], AD[7:0], INT, RDY
CS
, ALE,
RD
,
WR
, AD[7:0], INT, RDY
MODE 1
MODE 2
MODE 3
MODE 4
0
0
1
1
0
1
0
1
deMUXed
MUXed
deMUXed
MUXed
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